2024-09-09 08:52:07 +00:00
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/*
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* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
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* reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the NetLogic
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* license below:
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __NLM_HAL_SYS_H__
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#define __NLM_HAL_SYS_H__
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/**
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* @file_name sys.h
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* @author Netlogic Microsystems
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* @brief HAL for System configuration registers
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*/
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2024-09-09 08:57:42 +00:00
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#define SYS_CHIP_RESET 0x00
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#define SYS_POWER_ON_RESET_CFG 0x01
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#define SYS_EFUSE_DEVICE_CFG_STATUS0 0x02
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#define SYS_EFUSE_DEVICE_CFG_STATUS1 0x03
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#define SYS_EFUSE_DEVICE_CFG_STATUS2 0x04
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#define SYS_EFUSE_DEVICE_CFG3 0x05
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#define SYS_EFUSE_DEVICE_CFG4 0x06
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#define SYS_EFUSE_DEVICE_CFG5 0x07
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#define SYS_EFUSE_DEVICE_CFG6 0x08
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#define SYS_EFUSE_DEVICE_CFG7 0x09
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#define SYS_PLL_CTRL 0x0a
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#define SYS_CPU_RESET 0x0b
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#define SYS_CPU_NONCOHERENT_MODE 0x0d
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#define SYS_CORE_DFS_DIS_CTRL 0x0e
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#define SYS_CORE_DFS_RST_CTRL 0x0f
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#define SYS_CORE_DFS_BYP_CTRL 0x10
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#define SYS_CORE_DFS_PHA_CTRL 0x11
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#define SYS_CORE_DFS_DIV_INC_CTRL 0x12
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#define SYS_CORE_DFS_DIV_DEC_CTRL 0x13
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#define SYS_CORE_DFS_DIV_VALUE 0x14
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#define SYS_RESET 0x15
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#define SYS_DFS_DIS_CTRL 0x16
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#define SYS_DFS_RST_CTRL 0x17
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#define SYS_DFS_BYP_CTRL 0x18
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#define SYS_DFS_DIV_INC_CTRL 0x19
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#define SYS_DFS_DIV_DEC_CTRL 0x1a
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#define SYS_DFS_DIV_VALUE0 0x1b
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#define SYS_DFS_DIV_VALUE1 0x1c
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#define SYS_SENSE_AMP_DLY 0x1d
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#define SYS_SOC_SENSE_AMP_DLY 0x1e
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#define SYS_CTRL0 0x1f
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#define SYS_CTRL1 0x20
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#define SYS_TIMEOUT_BS1 0x21
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#define SYS_BYTE_SWAP 0x22
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#define SYS_VRM_VID 0x23
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#define SYS_PWR_RAM_CMD 0x24
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#define SYS_PWR_RAM_ADDR 0x25
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#define SYS_PWR_RAM_DATA0 0x26
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#define SYS_PWR_RAM_DATA1 0x27
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#define SYS_PWR_RAM_DATA2 0x28
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#define SYS_PWR_UCODE 0x29
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#define SYS_CPU0_PWR_STATUS 0x2a
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#define SYS_CPU1_PWR_STATUS 0x2b
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#define SYS_CPU2_PWR_STATUS 0x2c
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#define SYS_CPU3_PWR_STATUS 0x2d
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#define SYS_CPU4_PWR_STATUS 0x2e
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#define SYS_CPU5_PWR_STATUS 0x2f
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#define SYS_CPU6_PWR_STATUS 0x30
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#define SYS_CPU7_PWR_STATUS 0x31
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#define SYS_STATUS 0x32
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#define SYS_INT_POL 0x33
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#define SYS_INT_TYPE 0x34
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#define SYS_INT_STATUS 0x35
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#define SYS_INT_MASK0 0x36
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#define SYS_INT_MASK1 0x37
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#define SYS_UCO_S_ECC 0x38
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#define SYS_UCO_M_ECC 0x39
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#define SYS_UCO_ADDR 0x3a
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#define SYS_UCO_INSTR 0x3b
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#define SYS_MEM_BIST0 0x3c
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#define SYS_MEM_BIST1 0x3d
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#define SYS_MEM_BIST2 0x3e
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#define SYS_MEM_BIST3 0x3f
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#define SYS_MEM_BIST4 0x40
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#define SYS_MEM_BIST5 0x41
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#define SYS_MEM_BIST6 0x42
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#define SYS_MEM_BIST7 0x43
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#define SYS_MEM_BIST8 0x44
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#define SYS_MEM_BIST9 0x45
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#define SYS_MEM_BIST10 0x46
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#define SYS_MEM_BIST11 0x47
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#define SYS_MEM_BIST12 0x48
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#define SYS_SCRTCH0 0x49
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#define SYS_SCRTCH1 0x4a
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#define SYS_SCRTCH2 0x4b
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#define SYS_SCRTCH3 0x4c
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/* PLL registers XLP2XX */
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#define SYS_CPU_PLL_CTRL0(core) (0x1c0 + (core * 4))
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#define SYS_CPU_PLL_CTRL1(core) (0x1c1 + (core * 4))
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#define SYS_CPU_PLL_CTRL2(core) (0x1c2 + (core * 4))
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#define SYS_CPU_PLL_CTRL3(core) (0x1c3 + (core * 4))
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#define SYS_PLL_CTRL0 0x240
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#define SYS_PLL_CTRL1 0x241
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#define SYS_PLL_CTRL2 0x242
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#define SYS_PLL_CTRL3 0x243
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#define SYS_DMC_PLL_CTRL0 0x244
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#define SYS_DMC_PLL_CTRL1 0x245
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#define SYS_DMC_PLL_CTRL2 0x246
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#define SYS_DMC_PLL_CTRL3 0x247
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#define SYS_PLL_CTRL0_DEVX(x) (0x248 + (x) * 4)
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#define SYS_PLL_CTRL1_DEVX(x) (0x249 + (x) * 4)
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#define SYS_PLL_CTRL2_DEVX(x) (0x24a + (x) * 4)
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#define SYS_PLL_CTRL3_DEVX(x) (0x24b + (x) * 4)
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#define SYS_CPU_PLL_CHG_CTRL 0x288
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#define SYS_PLL_CHG_CTRL 0x289
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#define SYS_CLK_DEV_DIS 0x28a
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#define SYS_CLK_DEV_SEL 0x28b
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#define SYS_CLK_DEV_DIV 0x28c
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#define SYS_CLK_DEV_CHG 0x28d
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#define SYS_CLK_DEV_SEL_REG 0x28e
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#define SYS_CLK_DEV_DIV_REG 0x28f
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#define SYS_CPU_PLL_LOCK 0x29f
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#define SYS_SYS_PLL_LOCK 0x2a0
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#define SYS_PLL_MEM_CMD 0x2a1
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#define SYS_CPU_PLL_MEM_REQ 0x2a2
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#define SYS_SYS_PLL_MEM_REQ 0x2a3
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#define SYS_PLL_MEM_STAT 0x2a4
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/* PLL registers XLP9XX */
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#define SYS_9XX_CPU_PLL_CTRL0(core) (0xc0 + (core * 4))
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#define SYS_9XX_CPU_PLL_CTRL1(core) (0xc1 + (core * 4))
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#define SYS_9XX_CPU_PLL_CTRL2(core) (0xc2 + (core * 4))
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#define SYS_9XX_CPU_PLL_CTRL3(core) (0xc3 + (core * 4))
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#define SYS_9XX_DMC_PLL_CTRL0 0x140
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#define SYS_9XX_DMC_PLL_CTRL1 0x141
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#define SYS_9XX_DMC_PLL_CTRL2 0x142
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#define SYS_9XX_DMC_PLL_CTRL3 0x143
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#define SYS_9XX_PLL_CTRL0 0x144
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#define SYS_9XX_PLL_CTRL1 0x145
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#define SYS_9XX_PLL_CTRL2 0x146
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#define SYS_9XX_PLL_CTRL3 0x147
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#define SYS_9XX_PLL_CTRL0_DEVX(x) (0x148 + (x) * 4)
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#define SYS_9XX_PLL_CTRL1_DEVX(x) (0x149 + (x) * 4)
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#define SYS_9XX_PLL_CTRL2_DEVX(x) (0x14a + (x) * 4)
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#define SYS_9XX_PLL_CTRL3_DEVX(x) (0x14b + (x) * 4)
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#define SYS_9XX_CPU_PLL_CHG_CTRL 0x188
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#define SYS_9XX_PLL_CHG_CTRL 0x189
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#define SYS_9XX_CLK_DEV_DIS 0x18a
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#define SYS_9XX_CLK_DEV_SEL 0x18b
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#define SYS_9XX_CLK_DEV_DIV 0x18d
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#define SYS_9XX_CLK_DEV_CHG 0x18f
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/* Registers changed on 9XX */
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#define SYS_9XX_POWER_ON_RESET_CFG 0x00
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#define SYS_9XX_CHIP_RESET 0x01
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#define SYS_9XX_CPU_RESET 0x02
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#define SYS_9XX_CPU_NONCOHERENT_MODE 0x03
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/* XLP 9XX fuse block registers */
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#define FUSE_9XX_DEVCFG6 0xc6
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2024-09-09 08:52:07 +00:00
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#ifndef __ASSEMBLY__
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2024-09-09 08:57:42 +00:00
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#define nlm_read_sys_reg(b, r) nlm_read_reg(b, r)
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#define nlm_write_sys_reg(b, r, v) nlm_write_reg(b, r, v)
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#define nlm_get_sys_pcibase(node) nlm_pcicfg_base(cpu_is_xlp9xx() ? \
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XLP9XX_IO_SYS_OFFSET(node) : XLP_IO_SYS_OFFSET(node))
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#define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ)
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/* XLP9XX fuse block */
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#define nlm_get_fuse_pcibase(node) \
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nlm_pcicfg_base(XLP9XX_IO_FUSE_OFFSET(node))
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#define nlm_get_fuse_regbase(node) \
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(nlm_get_fuse_pcibase(node) + XLP_IO_PCI_HDRSZ)
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#define nlm_get_clock_pcibase(node) \
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nlm_pcicfg_base(XLP9XX_IO_CLOCK_OFFSET(node))
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#define nlm_get_clock_regbase(node) \
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(nlm_get_clock_pcibase(node) + XLP_IO_PCI_HDRSZ)
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2024-09-09 08:52:07 +00:00
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2024-09-09 08:57:42 +00:00
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unsigned int nlm_get_pic_frequency(int node);
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2024-09-09 08:52:07 +00:00
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#endif
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#endif
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