114 lines
4.0 KiB
C
114 lines
4.0 KiB
C
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/*
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* Copyright (c) 2003-2012 Broadcom Corporation
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* All Rights Reserved
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the Broadcom
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* license below:
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __NLM_HAL_PCIBUS_H__
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#define __NLM_HAL_PCIBUS_H__
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/* PCIE Memory and IO regions */
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#define PCIE_MEM_BASE 0xd0000000ULL
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#define PCIE_MEM_LIMIT 0xdfffffffULL
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#define PCIE_IO_BASE 0x14000000ULL
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#define PCIE_IO_LIMIT 0x15ffffffULL
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#define PCIE_BRIDGE_CMD 0x1
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#define PCIE_BRIDGE_MSI_CAP 0x14
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#define PCIE_BRIDGE_MSI_ADDRL 0x15
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#define PCIE_BRIDGE_MSI_ADDRH 0x16
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#define PCIE_BRIDGE_MSI_DATA 0x17
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/* XLP Global PCIE configuration space registers */
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#define PCIE_BYTE_SWAP_MEM_BASE 0x247
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#define PCIE_BYTE_SWAP_MEM_LIM 0x248
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#define PCIE_BYTE_SWAP_IO_BASE 0x249
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#define PCIE_BYTE_SWAP_IO_LIM 0x24A
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#define PCIE_BRIDGE_MSIX_ADDR_BASE 0x24F
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#define PCIE_BRIDGE_MSIX_ADDR_LIMIT 0x250
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#define PCIE_MSI_STATUS 0x25A
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#define PCIE_MSI_EN 0x25B
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#define PCIE_MSIX_STATUS 0x25D
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#define PCIE_INT_STATUS0 0x25F
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#define PCIE_INT_STATUS1 0x260
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#define PCIE_INT_EN0 0x261
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#define PCIE_INT_EN1 0x262
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/* XLP9XX has basic changes */
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#define PCIE_9XX_BYTE_SWAP_MEM_BASE 0x25c
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#define PCIE_9XX_BYTE_SWAP_MEM_LIM 0x25d
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#define PCIE_9XX_BYTE_SWAP_IO_BASE 0x25e
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#define PCIE_9XX_BYTE_SWAP_IO_LIM 0x25f
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#define PCIE_9XX_BRIDGE_MSIX_ADDR_BASE 0x264
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#define PCIE_9XX_BRIDGE_MSIX_ADDR_LIMIT 0x265
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#define PCIE_9XX_MSI_STATUS 0x283
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#define PCIE_9XX_MSI_EN 0x284
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/* 128 MSIX vectors available in 9xx */
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#define PCIE_9XX_MSIX_STATUS0 0x286
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#define PCIE_9XX_MSIX_STATUSX(n) (n + 0x286)
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#define PCIE_9XX_MSIX_VEC 0x296
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#define PCIE_9XX_MSIX_VECX(n) (n + 0x296)
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#define PCIE_9XX_INT_STATUS0 0x397
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#define PCIE_9XX_INT_STATUS1 0x398
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#define PCIE_9XX_INT_EN0 0x399
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#define PCIE_9XX_INT_EN1 0x39a
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/* other */
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#define PCIE_NLINKS 4
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/* MSI addresses */
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#define MSI_ADDR_BASE 0xfffee00000ULL
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#define MSI_ADDR_SZ 0x10000
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#define MSI_LINK_ADDR(n, l) (MSI_ADDR_BASE + \
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(PCIE_NLINKS * (n) + (l)) * MSI_ADDR_SZ)
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#define MSIX_ADDR_BASE 0xfffef00000ULL
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#define MSIX_LINK_ADDR(n, l) (MSIX_ADDR_BASE + \
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(PCIE_NLINKS * (n) + (l)) * MSI_ADDR_SZ)
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#ifndef __ASSEMBLY__
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#define nlm_read_pcie_reg(b, r) nlm_read_reg(b, r)
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#define nlm_write_pcie_reg(b, r, v) nlm_write_reg(b, r, v)
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#define nlm_get_pcie_base(node, inst) nlm_pcicfg_base(cpu_is_xlp9xx() ? \
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XLP9XX_IO_PCIE_OFFSET(node, inst) : XLP_IO_PCIE_OFFSET(node, inst))
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#ifdef CONFIG_PCI_MSI
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void xlp_init_node_msi_irqs(int node, int link);
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#else
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static inline void xlp_init_node_msi_irqs(int node, int link) {}
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#endif
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struct pci_dev *xlp_get_pcie_link(const struct pci_dev *dev);
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#endif
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#endif /* __NLM_HAL_PCIBUS_H__ */
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