2024-09-09 08:52:07 +00:00
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/*
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* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
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* reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the NetLogic
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* license below:
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __NLM_HAL_BRIDGE_H__
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#define __NLM_HAL_BRIDGE_H__
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/**
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* @file_name mio.h
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* @author Netlogic Microsystems
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* @brief Basic definitions of XLP memory and io subsystem
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*/
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/*
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* BRIDGE specific registers
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*
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* These registers start after the PCIe header, which has 0x40
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* standard entries
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*/
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#define BRIDGE_MODE 0x00
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#define BRIDGE_PCI_CFG_BASE 0x01
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#define BRIDGE_PCI_CFG_LIMIT 0x02
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#define BRIDGE_PCIE_CFG_BASE 0x03
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#define BRIDGE_PCIE_CFG_LIMIT 0x04
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#define BRIDGE_BUSNUM_BAR0 0x05
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#define BRIDGE_BUSNUM_BAR1 0x06
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#define BRIDGE_BUSNUM_BAR2 0x07
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#define BRIDGE_BUSNUM_BAR3 0x08
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#define BRIDGE_BUSNUM_BAR4 0x09
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#define BRIDGE_BUSNUM_BAR5 0x0a
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#define BRIDGE_BUSNUM_BAR6 0x0b
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#define BRIDGE_FLASH_BAR0 0x0c
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#define BRIDGE_FLASH_BAR1 0x0d
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#define BRIDGE_FLASH_BAR2 0x0e
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#define BRIDGE_FLASH_BAR3 0x0f
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#define BRIDGE_FLASH_LIMIT0 0x10
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#define BRIDGE_FLASH_LIMIT1 0x11
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#define BRIDGE_FLASH_LIMIT2 0x12
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#define BRIDGE_FLASH_LIMIT3 0x13
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#define BRIDGE_DRAM_BAR(i) (0x14 + (i))
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#define BRIDGE_DRAM_LIMIT(i) (0x1c + (i))
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#define BRIDGE_DRAM_NODE_TRANSLN(i) (0x24 + (i))
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#define BRIDGE_DRAM_CHNL_TRANSLN(i) (0x2c + (i))
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2024-09-09 08:52:07 +00:00
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#define BRIDGE_PCIEMEM_BASE0 0x34
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#define BRIDGE_PCIEMEM_BASE1 0x35
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#define BRIDGE_PCIEMEM_BASE2 0x36
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#define BRIDGE_PCIEMEM_BASE3 0x37
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#define BRIDGE_PCIEMEM_LIMIT0 0x38
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#define BRIDGE_PCIEMEM_LIMIT1 0x39
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#define BRIDGE_PCIEMEM_LIMIT2 0x3a
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#define BRIDGE_PCIEMEM_LIMIT3 0x3b
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#define BRIDGE_PCIEIO_BASE0 0x3c
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#define BRIDGE_PCIEIO_BASE1 0x3d
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#define BRIDGE_PCIEIO_BASE2 0x3e
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#define BRIDGE_PCIEIO_BASE3 0x3f
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#define BRIDGE_PCIEIO_LIMIT0 0x40
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#define BRIDGE_PCIEIO_LIMIT1 0x41
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#define BRIDGE_PCIEIO_LIMIT2 0x42
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#define BRIDGE_PCIEIO_LIMIT3 0x43
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#define BRIDGE_PCIEMEM_BASE4 0x44
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#define BRIDGE_PCIEMEM_BASE5 0x45
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#define BRIDGE_PCIEMEM_BASE6 0x46
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#define BRIDGE_PCIEMEM_LIMIT4 0x47
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#define BRIDGE_PCIEMEM_LIMIT5 0x48
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#define BRIDGE_PCIEMEM_LIMIT6 0x49
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#define BRIDGE_PCIEIO_BASE4 0x4a
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#define BRIDGE_PCIEIO_BASE5 0x4b
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#define BRIDGE_PCIEIO_BASE6 0x4c
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#define BRIDGE_PCIEIO_LIMIT4 0x4d
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#define BRIDGE_PCIEIO_LIMIT5 0x4e
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#define BRIDGE_PCIEIO_LIMIT6 0x4f
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#define BRIDGE_NBU_EVENT_CNT_CTL 0x50
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#define BRIDGE_EVNTCTR1_LOW 0x51
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#define BRIDGE_EVNTCTR1_HI 0x52
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#define BRIDGE_EVNT_CNT_CTL2 0x53
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#define BRIDGE_EVNTCTR2_LOW 0x54
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#define BRIDGE_EVNTCTR2_HI 0x55
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#define BRIDGE_TRACEBUF_MATCH0 0x56
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#define BRIDGE_TRACEBUF_MATCH1 0x57
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#define BRIDGE_TRACEBUF_MATCH_LOW 0x58
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#define BRIDGE_TRACEBUF_MATCH_HI 0x59
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#define BRIDGE_TRACEBUF_CTRL 0x5a
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#define BRIDGE_TRACEBUF_INIT 0x5b
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#define BRIDGE_TRACEBUF_ACCESS 0x5c
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#define BRIDGE_TRACEBUF_READ_DATA0 0x5d
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#define BRIDGE_TRACEBUF_READ_DATA1 0x5d
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#define BRIDGE_TRACEBUF_READ_DATA2 0x5f
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#define BRIDGE_TRACEBUF_READ_DATA3 0x60
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#define BRIDGE_TRACEBUF_STATUS 0x61
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#define BRIDGE_ADDRESS_ERROR0 0x62
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#define BRIDGE_ADDRESS_ERROR1 0x63
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#define BRIDGE_ADDRESS_ERROR2 0x64
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#define BRIDGE_TAG_ECC_ADDR_ERROR0 0x65
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#define BRIDGE_TAG_ECC_ADDR_ERROR1 0x66
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#define BRIDGE_TAG_ECC_ADDR_ERROR2 0x67
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#define BRIDGE_LINE_FLUSH0 0x68
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#define BRIDGE_LINE_FLUSH1 0x69
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#define BRIDGE_NODE_ID 0x6a
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#define BRIDGE_ERROR_INTERRUPT_EN 0x6b
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#define BRIDGE_PCIE0_WEIGHT 0x2c0
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#define BRIDGE_PCIE1_WEIGHT 0x2c1
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#define BRIDGE_PCIE2_WEIGHT 0x2c2
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#define BRIDGE_PCIE3_WEIGHT 0x2c3
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#define BRIDGE_USB_WEIGHT 0x2c4
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#define BRIDGE_NET_WEIGHT 0x2c5
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#define BRIDGE_POE_WEIGHT 0x2c6
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#define BRIDGE_CMS_WEIGHT 0x2c7
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#define BRIDGE_DMAENG_WEIGHT 0x2c8
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#define BRIDGE_SEC_WEIGHT 0x2c9
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#define BRIDGE_COMP_WEIGHT 0x2ca
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#define BRIDGE_GIO_WEIGHT 0x2cb
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#define BRIDGE_FLASH_WEIGHT 0x2cc
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2024-09-09 08:57:42 +00:00
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/* FIXME verify */
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#define BRIDGE_9XX_FLASH_BAR(i) (0x11 + (i))
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#define BRIDGE_9XX_FLASH_BAR_LIMIT(i) (0x15 + (i))
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#define BRIDGE_9XX_DRAM_BAR(i) (0x19 + (i))
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#define BRIDGE_9XX_DRAM_LIMIT(i) (0x29 + (i))
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#define BRIDGE_9XX_DRAM_NODE_TRANSLN(i) (0x39 + (i))
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#define BRIDGE_9XX_DRAM_CHNL_TRANSLN(i) (0x49 + (i))
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#define BRIDGE_9XX_ADDRESS_ERROR0 0x9d
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#define BRIDGE_9XX_ADDRESS_ERROR1 0x9e
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#define BRIDGE_9XX_ADDRESS_ERROR2 0x9f
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#define BRIDGE_9XX_PCIEMEM_BASE0 0x59
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#define BRIDGE_9XX_PCIEMEM_BASE1 0x5a
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#define BRIDGE_9XX_PCIEMEM_BASE2 0x5b
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#define BRIDGE_9XX_PCIEMEM_BASE3 0x5c
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#define BRIDGE_9XX_PCIEMEM_LIMIT0 0x5d
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#define BRIDGE_9XX_PCIEMEM_LIMIT1 0x5e
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#define BRIDGE_9XX_PCIEMEM_LIMIT2 0x5f
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#define BRIDGE_9XX_PCIEMEM_LIMIT3 0x60
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#define BRIDGE_9XX_PCIEIO_BASE0 0x61
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#define BRIDGE_9XX_PCIEIO_BASE1 0x62
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#define BRIDGE_9XX_PCIEIO_BASE2 0x63
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#define BRIDGE_9XX_PCIEIO_BASE3 0x64
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#define BRIDGE_9XX_PCIEIO_LIMIT0 0x65
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#define BRIDGE_9XX_PCIEIO_LIMIT1 0x66
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#define BRIDGE_9XX_PCIEIO_LIMIT2 0x67
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#define BRIDGE_9XX_PCIEIO_LIMIT3 0x68
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2024-09-09 08:52:07 +00:00
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#ifndef __ASSEMBLY__
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#define nlm_read_bridge_reg(b, r) nlm_read_reg(b, r)
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#define nlm_write_bridge_reg(b, r, v) nlm_write_reg(b, r, v)
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#define nlm_get_bridge_pcibase(node) nlm_pcicfg_base(cpu_is_xlp9xx() ? \
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XLP9XX_IO_BRIDGE_OFFSET(node) : XLP_IO_BRIDGE_OFFSET(node))
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#define nlm_get_bridge_regbase(node) \
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(nlm_get_bridge_pcibase(node) + XLP_IO_PCI_HDRSZ)
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#endif /* __ASSEMBLY__ */
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#endif /* __NLM_HAL_BRIDGE_H__ */
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