2024-09-09 08:52:07 +00:00
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Chris Dearman (chris@mips.com)
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* Copyright (C) 2007 Mips Technologies, Inc.
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2024-09-09 08:57:42 +00:00
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* Copyright (C) 2014 Imagination Technologies Ltd.
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2024-09-09 08:52:07 +00:00
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*/
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#ifndef __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H
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#define __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H
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2024-09-09 08:57:42 +00:00
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#include <asm/regdef.h>
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#include <asm/mipsregs.h>
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/*
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* Prepare segments for EVA boot:
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*
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* This is in case the processor boots in legacy configuration
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* (SI_EVAReset is de-asserted and CONFIG5.K == 0)
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*
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* ========================= Mappings =============================
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* Virtual memory Physical memory Mapping
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* 0x00000000 - 0x7fffffff 0x80000000 - 0xfffffffff MUSUK (kuseg)
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* Flat 2GB physical memory
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*
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* 0x80000000 - 0x9fffffff 0x00000000 - 0x1ffffffff MUSUK (kseg0)
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* 0xa0000000 - 0xbf000000 0x00000000 - 0x1ffffffff MUSUK (kseg1)
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* 0xc0000000 - 0xdfffffff - MK (kseg2)
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* 0xe0000000 - 0xffffffff - MK (kseg3)
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*
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*
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* Lowmem is expanded to 2GB
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*
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* The following code uses the t0, t1, t2 and ra registers without
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* previously preserving them.
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*
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*/
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.macro platform_eva_init
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.set push
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.set reorder
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/*
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* Get Config.K0 value and use it to program
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* the segmentation registers
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*/
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mfc0 t1, CP0_CONFIG
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andi t1, 0x7 /* CCA */
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move t2, t1
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ins t2, t1, 16, 3
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/* SegCtl0 */
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li t0, ((MIPS_SEGCFG_MK << MIPS_SEGCFG_AM_SHIFT) | \
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(0 << MIPS_SEGCFG_PA_SHIFT) | \
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(1 << MIPS_SEGCFG_EU_SHIFT)) | \
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(((MIPS_SEGCFG_MK << MIPS_SEGCFG_AM_SHIFT) | \
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(0 << MIPS_SEGCFG_PA_SHIFT) | \
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(1 << MIPS_SEGCFG_EU_SHIFT)) << 16)
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or t0, t2
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mtc0 t0, $5, 2
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/* SegCtl1 */
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li t0, ((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) | \
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(0 << MIPS_SEGCFG_PA_SHIFT) | \
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(2 << MIPS_SEGCFG_C_SHIFT) | \
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(1 << MIPS_SEGCFG_EU_SHIFT)) | \
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(((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) | \
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(0 << MIPS_SEGCFG_PA_SHIFT) | \
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(1 << MIPS_SEGCFG_EU_SHIFT)) << 16)
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ins t0, t1, 16, 3
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mtc0 t0, $5, 3
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/* SegCtl2 */
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li t0, ((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) | \
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(6 << MIPS_SEGCFG_PA_SHIFT) | \
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(1 << MIPS_SEGCFG_EU_SHIFT)) | \
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(((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) | \
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(4 << MIPS_SEGCFG_PA_SHIFT) | \
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(1 << MIPS_SEGCFG_EU_SHIFT)) << 16)
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or t0, t2
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mtc0 t0, $5, 4
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jal mips_ihb
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mfc0 t0, $16, 5
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li t2, 0x40000000 /* K bit */
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or t0, t0, t2
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mtc0 t0, $16, 5
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sync
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jal mips_ihb
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.set pop
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.endm
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2024-09-09 08:52:07 +00:00
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.macro kernel_entry_setup
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2024-09-09 08:57:42 +00:00
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#ifdef CONFIG_EVA
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sync
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ehb
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mfc0 t1, CP0_CONFIG
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bgez t1, 9f
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2024-09-09 08:52:07 +00:00
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mfc0 t0, CP0_CONFIG, 1
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bgez t0, 9f
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mfc0 t0, CP0_CONFIG, 2
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bgez t0, 9f
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mfc0 t0, CP0_CONFIG, 3
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2024-09-09 08:57:42 +00:00
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sll t0, t0, 6 /* SC bit */
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bgez t0, 9f
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platform_eva_init
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b 0f
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2024-09-09 08:52:07 +00:00
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9:
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/* Assume we came from YAMON... */
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PTR_LA v0, 0x9fc00534 /* YAMON print */
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lw v0, (v0)
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move a0, zero
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2024-09-09 08:57:42 +00:00
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PTR_LA a1, nonsc_processor
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2024-09-09 08:52:07 +00:00
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jal v0
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PTR_LA v0, 0x9fc00520 /* YAMON exit */
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lw v0, (v0)
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li a0, 1
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jal v0
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1: b 1b
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2024-09-09 08:57:42 +00:00
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nop
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2024-09-09 08:52:07 +00:00
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__INITDATA
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2024-09-09 08:57:42 +00:00
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nonsc_processor:
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.asciz "EVA kernel requires a MIPS core with Segment Control implemented\n"
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2024-09-09 08:52:07 +00:00
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__FINIT
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2024-09-09 08:57:42 +00:00
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#endif /* CONFIG_EVA */
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2024-09-09 08:52:07 +00:00
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0:
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.endm
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/*
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* Do SMP slave processor setup necessary before we can safely execute C code.
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*/
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.macro smp_slave_setup
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2024-09-09 08:57:42 +00:00
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#ifdef CONFIG_EVA
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sync
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ehb
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platform_eva_init
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#endif
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2024-09-09 08:52:07 +00:00
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.endm
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#endif /* __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H */
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