35 lines
965 B
C
35 lines
965 B
C
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/*
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* Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
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*
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* Loongson 1 Clock Register Definitions.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef __ASM_MACH_LOONGSON1_REGS_CLK_H
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#define __ASM_MACH_LOONGSON1_REGS_CLK_H
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#define LS1X_CLK_REG(x) \
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((void __iomem *)KSEG1ADDR(LS1X_CLK_BASE + (x)))
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#define LS1X_CLK_PLL_FREQ LS1X_CLK_REG(0x0)
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#define LS1X_CLK_PLL_DIV LS1X_CLK_REG(0x4)
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/* Clock PLL Divisor Register Bits */
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#define DIV_DC_EN (0x1 << 31)
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#define DIV_CPU_EN (0x1 << 25)
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#define DIV_DDR_EN (0x1 << 19)
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#define DIV_DC_SHIFT 26
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#define DIV_CPU_SHIFT 20
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#define DIV_DDR_SHIFT 14
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#define DIV_DC_WIDTH 5
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#define DIV_CPU_WIDTH 5
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#define DIV_DDR_WIDTH 5
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#endif /* __ASM_MACH_LOONGSON1_REGS_CLK_H */
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