2024-09-09 08:52:07 +00:00
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/*
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* Copyright 2008-2009 Analog Devices Inc.
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*
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2024-09-09 08:57:42 +00:00
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* Licensed under the Clear BSD license or the GPL-2 (or later)
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2024-09-09 08:52:07 +00:00
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*/
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#ifndef _DEF_BF518_H
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#define _DEF_BF518_H
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/* BF518 is BF516 + IEEE-1588 */
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#include "defBF516.h"
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/* PTP TSYNC Registers */
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#define EMAC_PTP_CTL 0xFFC030A0 /* PTP Block Control */
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#define EMAC_PTP_IE 0xFFC030A4 /* PTP Block Interrupt Enable */
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#define EMAC_PTP_ISTAT 0xFFC030A8 /* PTP Block Interrupt Status */
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#define EMAC_PTP_FOFF 0xFFC030AC /* PTP Filter offset Register */
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#define EMAC_PTP_FV1 0xFFC030B0 /* PTP Filter Value Register 1 */
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#define EMAC_PTP_FV2 0xFFC030B4 /* PTP Filter Value Register 2 */
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#define EMAC_PTP_FV3 0xFFC030B8 /* PTP Filter Value Register 3 */
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#define EMAC_PTP_ADDEND 0xFFC030BC /* PTP Addend for Frequency Compensation */
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#define EMAC_PTP_ACCR 0xFFC030C0 /* PTP Accumulator for Frequency Compensation */
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#define EMAC_PTP_OFFSET 0xFFC030C4 /* PTP Time Offset Register */
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#define EMAC_PTP_TIMELO 0xFFC030C8 /* PTP Precision Clock Time Low */
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#define EMAC_PTP_TIMEHI 0xFFC030CC /* PTP Precision Clock Time High */
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#define EMAC_PTP_RXSNAPLO 0xFFC030D0 /* PTP Receive Snapshot Register Low */
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#define EMAC_PTP_RXSNAPHI 0xFFC030D4 /* PTP Receive Snapshot Register High */
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#define EMAC_PTP_TXSNAPLO 0xFFC030D8 /* PTP Transmit Snapshot Register Low */
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#define EMAC_PTP_TXSNAPHI 0xFFC030DC /* PTP Transmit Snapshot Register High */
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#define EMAC_PTP_ALARMLO 0xFFC030E0 /* PTP Alarm time Low */
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#define EMAC_PTP_ALARMHI 0xFFC030E4 /* PTP Alarm time High */
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#define EMAC_PTP_ID_OFF 0xFFC030E8 /* PTP Capture ID offset register */
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#define EMAC_PTP_ID_SNAP 0xFFC030EC /* PTP Capture ID register */
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#define EMAC_PTP_PPS_STARTLO 0xFFC030F0 /* PPS Start Time Low */
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#define EMAC_PTP_PPS_STARTHI 0xFFC030F4 /* PPS Start Time High */
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#define EMAC_PTP_PPS_PERIOD 0xFFC030F8 /* PPS Count Register */
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/* Bit masks for EMAC_PTP_CTL */
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#define PTP_EN 0x1 /* Enable the PTP_TSYNC module */
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#define TL 0x2 /* Timestamp lock control */
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#define ASEN 0x10 /* Auxiliary snapshot control */
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#define PPSEN 0x80 /* Pulse-per-second (PPS) control */
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#define CKOEN 0x2000 /* Clock output control */
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/* Bit masks for EMAC_PTP_IE */
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#define ALIE 0x1 /* Alarm interrupt enable */
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#define RXEIE 0x2 /* Receive event interrupt enable */
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#define RXGIE 0x4 /* Receive general interrupt enable */
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#define TXIE 0x8 /* Transmit interrupt enable */
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#define RXOVE 0x10 /* Receive overrun error interrupt enable */
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#define TXOVE 0x20 /* Transmit overrun error interrupt enable */
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#define ASIE 0x40 /* Auxiliary snapshot interrupt enable */
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/* Bit masks for EMAC_PTP_ISTAT */
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#define ALS 0x1 /* Alarm status */
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#define RXEL 0x2 /* Receive event interrupt status */
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#define RXGL 0x4 /* Receive general interrupt status */
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#define TXTL 0x8 /* Transmit snapshot status */
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#define RXOV 0x10 /* Receive snapshot overrun status */
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#define TXOV 0x20 /* Transmit snapshot overrun status */
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#define ASL 0x40 /* Auxiliary snapshot interrupt status */
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#endif /* _DEF_BF518_H */
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