2024-09-09 08:52:07 +00:00
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/*
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* Copyright (c) 2003 ARM Limited
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* All Rights Reserved
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2024-09-09 08:57:42 +00:00
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* Copyright (c) 2010, 2012, 2014, 2016 The Linux Foundation. All rights reserved.
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2024-09-09 08:52:07 +00:00
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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2024-09-09 08:57:42 +00:00
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.arm
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2024-09-09 08:52:07 +00:00
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__CPUINIT
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/*
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* MSM specific entry point for secondary CPUs. This provides
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* a "holding pen" into which all secondary cores are held until we're
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* ready for them to initialise.
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*
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* This is executing in physical space with cache's off.
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*/
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ENTRY(msm_secondary_startup)
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2024-09-09 08:57:42 +00:00
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THUMB( adr r9, BSYM(2f) ) @ Kernel is always entered in ARM.
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THUMB( bx r9 ) @ If this is a Thumb-2 kernel,
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THUMB( .thumb ) @ switch to Thumb now.
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THUMB(2: )
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2024-09-09 08:52:07 +00:00
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mrc p15, 0, r0, c0, c0, 5 @ MPIDR
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2024-09-09 08:57:42 +00:00
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bic r0, #0xff000000 @ What CPU am I
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2024-09-09 08:52:07 +00:00
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adr r4, 1f @ address of
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ldmia r4, {r5, r6} @ load curr addr and pen_rel addr
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sub r4, r4, r5 @ determine virtual/phys offsets
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add r6, r6, r4 @ apply
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pen:
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ldr r7, [r6] @ pen_rel has cpu to remove from reset
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cmp r7, r0 @ are we lucky?
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bne pen
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/*
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* we've been released from the holding pen: secondary_stack
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* should now contain the SVC stack for this core
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*/
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b secondary_startup
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ENDPROC(msm_secondary_startup)
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1: .long .
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.long pen_release
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