205 lines
5.6 KiB
C
205 lines
5.6 KiB
C
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/*
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* This file contains the hardware definitions of the Cirrus Logic
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* ARM7 CLPS711X internal registers.
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*
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* Copyright (C) 2000 Deep Blue Solutions Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __MACH_CLPS711X_H
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#define __MACH_CLPS711X_H
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#include <linux/mfd/syscon/clps711x.h>
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#define CLPS711X_PHYS_BASE (0x80000000)
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#define PADR (0x0000)
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#define PBDR (0x0001)
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#define PCDR (0x0002)
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#define PDDR (0x0003)
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#define PADDR (0x0040)
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#define PBDDR (0x0041)
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#define PCDDR (0x0042)
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#define PDDDR (0x0043)
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#define PEDR (0x0083)
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#define PEDDR (0x00c3)
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#define SYSCON1 (0x0100)
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#define SYSFLG1 (0x0140)
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#define MEMCFG1 (0x0180)
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#define MEMCFG2 (0x01c0)
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#define DRFPR (0x0200)
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#define LCDCON (0x02c0)
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#define TC1D (0x0300)
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#define TC2D (0x0340)
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#define RTCDR (0x0380)
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#define RTCMR (0x03c0)
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#define PMPCON (0x0400)
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#define CODR (0x0440)
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#define UARTDR1 (0x0480)
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#define UBRLCR1 (0x04c0)
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#define SYNCIO (0x0500)
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#define PALLSW (0x0540)
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#define PALMSW (0x0580)
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#define STFCLR (0x05c0)
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#define HALT (0x0800)
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#define STDBY (0x0840)
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#define FBADDR (0x1000)
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#define SYSCON2 (0x1100)
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#define SYSFLG2 (0x1140)
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#define UARTDR2 (0x1480)
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#define UBRLCR2 (0x14c0)
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#define SS2DR (0x1500)
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#define SS2POP (0x16c0)
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#define DAIR (0x2000)
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#define DAIDR0 (0x2040)
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#define DAIDR1 (0x2080)
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#define DAIDR2 (0x20c0)
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#define DAISR (0x2100)
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#define SYSCON3 (0x2200)
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#define LEDFLSH (0x22c0)
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#define SDCONF (0x2300)
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#define SDRFPR (0x2340)
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#define UNIQID (0x2440)
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#define DAI64FS (0x2600)
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#define PLLW (0x2610)
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#define PLLR (0xa5a8)
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#define RANDID0 (0x2700)
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#define RANDID1 (0x2704)
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#define RANDID2 (0x2708)
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#define RANDID3 (0x270c)
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#define LCDCON_GSEN (1 << 30)
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#define LCDCON_GSMD (1 << 31)
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/* common bits: UARTDR1 / UARTDR2 */
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#define UARTDR_FRMERR (1 << 8)
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#define UARTDR_PARERR (1 << 9)
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#define UARTDR_OVERR (1 << 10)
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/* common bits: UBRLCR1 / UBRLCR2 */
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#define UBRLCR_BAUD_MASK ((1 << 12) - 1)
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#define UBRLCR_BREAK (1 << 12)
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#define UBRLCR_PRTEN (1 << 13)
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#define UBRLCR_EVENPRT (1 << 14)
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#define UBRLCR_XSTOP (1 << 15)
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#define UBRLCR_FIFOEN (1 << 16)
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#define UBRLCR_WRDLEN5 (0 << 17)
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#define UBRLCR_WRDLEN6 (1 << 17)
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#define UBRLCR_WRDLEN7 (2 << 17)
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#define UBRLCR_WRDLEN8 (3 << 17)
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#define UBRLCR_WRDLEN_MASK (3 << 17)
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#define SYNCIO_FRMLEN(x) (((x) & 0x1f) << 8)
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#define SYNCIO_SMCKEN (1 << 13)
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#define SYNCIO_TXFRMEN (1 << 14)
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#define DAIR_RESERVED (0x0404)
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#define DAIR_DAIEN (1 << 16)
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#define DAIR_ECS (1 << 17)
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#define DAIR_LCTM (1 << 19)
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#define DAIR_LCRM (1 << 20)
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#define DAIR_RCTM (1 << 21)
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#define DAIR_RCRM (1 << 22)
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#define DAIR_LBM (1 << 23)
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#define DAIDR2_FIFOEN (1 << 15)
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#define DAIDR2_FIFOLEFT (0x0d << 16)
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#define DAIDR2_FIFORIGHT (0x11 << 16)
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#define DAISR_RCTS (1 << 0)
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#define DAISR_RCRS (1 << 1)
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#define DAISR_LCTS (1 << 2)
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#define DAISR_LCRS (1 << 3)
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#define DAISR_RCTU (1 << 4)
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#define DAISR_RCRO (1 << 5)
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#define DAISR_LCTU (1 << 6)
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#define DAISR_LCRO (1 << 7)
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#define DAISR_RCNF (1 << 8)
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#define DAISR_RCNE (1 << 9)
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#define DAISR_LCNF (1 << 10)
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#define DAISR_LCNE (1 << 11)
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#define DAISR_FIFO (1 << 12)
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#define DAI64FS_I2SF64 (1 << 0)
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#define DAI64FS_AUDIOCLKEN (1 << 1)
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#define DAI64FS_AUDIOCLKSRC (1 << 2)
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#define DAI64FS_MCLK256EN (1 << 3)
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#define DAI64FS_LOOPBACK (1 << 5)
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#define SDCONF_ACTIVE (1 << 10)
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#define SDCONF_CLKCTL (1 << 9)
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#define SDCONF_WIDTH_4 (0 << 7)
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#define SDCONF_WIDTH_8 (1 << 7)
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#define SDCONF_WIDTH_16 (2 << 7)
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#define SDCONF_WIDTH_32 (3 << 7)
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#define SDCONF_SIZE_16 (0 << 5)
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#define SDCONF_SIZE_64 (1 << 5)
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#define SDCONF_SIZE_128 (2 << 5)
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#define SDCONF_SIZE_256 (3 << 5)
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#define SDCONF_CASLAT_2 (2)
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#define SDCONF_CASLAT_3 (3)
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#define MEMCFG_BUS_WIDTH_32 (1)
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#define MEMCFG_BUS_WIDTH_16 (0)
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#define MEMCFG_BUS_WIDTH_8 (3)
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#define MEMCFG_SQAEN (1 << 6)
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#define MEMCFG_CLKENB (1 << 7)
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#define MEMCFG_WAITSTATE_8_3 (0 << 2)
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#define MEMCFG_WAITSTATE_7_3 (1 << 2)
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#define MEMCFG_WAITSTATE_6_3 (2 << 2)
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#define MEMCFG_WAITSTATE_5_3 (3 << 2)
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#define MEMCFG_WAITSTATE_4_2 (4 << 2)
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#define MEMCFG_WAITSTATE_3_2 (5 << 2)
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#define MEMCFG_WAITSTATE_2_2 (6 << 2)
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#define MEMCFG_WAITSTATE_1_2 (7 << 2)
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#define MEMCFG_WAITSTATE_8_1 (8 << 2)
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#define MEMCFG_WAITSTATE_7_1 (9 << 2)
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#define MEMCFG_WAITSTATE_6_1 (10 << 2)
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#define MEMCFG_WAITSTATE_5_1 (11 << 2)
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#define MEMCFG_WAITSTATE_4_0 (12 << 2)
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#define MEMCFG_WAITSTATE_3_0 (13 << 2)
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#define MEMCFG_WAITSTATE_2_0 (14 << 2)
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#define MEMCFG_WAITSTATE_1_0 (15 << 2)
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/* INTSR1 Interrupts */
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#define IRQ_CSINT (4)
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#define IRQ_EINT1 (5)
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#define IRQ_EINT2 (6)
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#define IRQ_EINT3 (7)
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#define IRQ_TC1OI (8)
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#define IRQ_TC2OI (9)
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#define IRQ_RTCMI (10)
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#define IRQ_TINT (11)
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#define IRQ_UTXINT1 (12)
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#define IRQ_URXINT1 (13)
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#define IRQ_UMSINT (14)
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#define IRQ_SSEOTI (15)
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/* INTSR2 Interrupts */
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#define IRQ_KBDINT (16 + 0)
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#define IRQ_SS2RX (16 + 1)
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#define IRQ_SS2TX (16 + 2)
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#define IRQ_UTXINT2 (16 + 12)
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#define IRQ_URXINT2 (16 + 13)
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/* INTSR3 Interrupts */
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#define IRQ_DAIINT (32 + 0)
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#endif /* __MACH_CLPS711X_H */
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