746 lines
17 KiB
Plaintext
746 lines
17 KiB
Plaintext
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/*
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* Copyright 2013 Linaro Ltd.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include "ste-nomadik-pinctrl.dtsi"
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/ {
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soc {
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pinctrl {
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/* Settings for all UART default and sleep states */
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uart0 {
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uart0_default_mode: uart0_default {
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default_mux {
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ste,function = "u0";
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ste,pins = "u0_a_1";
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};
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default_cfg1 {
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ste,pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
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ste,config = <&in_pu>;
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};
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default_cfg2 {
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ste,pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */
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ste,config = <&out_hi>;
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};
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};
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uart0_sleep_mode: uart0_sleep {
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sleep_cfg1 {
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ste,pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
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ste,config = <&slpm_in_wkup_pdis>;
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};
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sleep_cfg2 {
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ste,pins = "GPIO1_AJ3"; /* RTS */
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ste,config = <&slpm_out_hi_wkup_pdis>;
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};
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sleep_cfg3 {
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ste,pins = "GPIO3_AH3"; /* TXD */
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ste,config = <&slpm_out_wkup_pdis>;
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};
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};
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};
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uart1 {
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uart1_default_mode: uart1_default {
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default_mux {
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ste,function = "u1";
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ste,pins = "u1rxtx_a_1";
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};
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default_cfg1 {
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ste,pins = "GPIO4_AH6"; /* RXD */
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ste,config = <&in_pu>;
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};
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default_cfg2 {
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ste,pins = "GPIO5_AG6"; /* TXD */
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ste,config = <&out_hi>;
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};
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};
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uart1_sleep_mode: uart1_sleep {
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sleep_cfg1 {
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ste,pins = "GPIO4_AH6"; /* RXD */
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ste,config = <&slpm_in_wkup_pdis>;
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};
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sleep_cfg2 {
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ste,pins = "GPIO5_AG6"; /* TXD */
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ste,config = <&slpm_out_wkup_pdis>;
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};
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};
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};
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uart2 {
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uart2_default_mode: uart2_default {
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default_mux {
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ste,function = "u2";
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ste,pins = "u2rxtx_c_1";
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};
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default_cfg1 {
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ste,pins = "GPIO29_W2"; /* RXD */
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ste,config = <&in_pu>;
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};
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default_cfg2 {
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ste,pins = "GPIO30_W3"; /* TXD */
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ste,config = <&out_hi>;
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};
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};
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uart2_sleep_mode: uart2_sleep {
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sleep_cfg1 {
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ste,pins = "GPIO29_W2"; /* RXD */
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ste,config = <&in_wkup_pdis>;
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};
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sleep_cfg2 {
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ste,pins = "GPIO30_W3"; /* TXD */
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ste,config = <&out_wkup_pdis>;
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};
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};
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};
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/* Settings for all I2C default and sleep states */
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i2c0 {
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i2c0_default_mode: i2c_default {
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default_mux {
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ste,function = "i2c0";
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ste,pins = "i2c0_a_1";
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};
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default_cfg1 {
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ste,pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
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ste,config = <&in_pu>;
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};
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};
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i2c0_sleep_mode: i2c_sleep {
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sleep_cfg1 {
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ste,pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
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ste,config = <&slpm_in_wkup_pdis>;
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};
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};
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};
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i2c1 {
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i2c1_default_mode: i2c_default {
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default_mux {
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ste,function = "i2c1";
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ste,pins = "i2c1_b_2";
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};
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default_cfg1 {
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ste,pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
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ste,config = <&in_pu>;
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};
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};
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i2c1_sleep_mode: i2c_sleep {
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sleep_cfg1 {
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ste,pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
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ste,config = <&slpm_in_wkup_pdis>;
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};
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};
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};
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i2c2 {
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i2c2_default_mode: i2c_default {
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default_mux {
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ste,function = "i2c2";
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ste,pins = "i2c2_b_2";
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};
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default_cfg1 {
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ste,pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
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ste,config = <&in_pu>;
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};
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};
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i2c2_sleep_mode: i2c_sleep {
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sleep_cfg1 {
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ste,pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
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ste,config = <&slpm_in_wkup_pdis>;
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};
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};
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};
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i2c3 {
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i2c3_default_mode: i2c_default {
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default_mux {
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ste,function = "i2c3";
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ste,pins = "i2c3_c_2";
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};
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default_cfg1 {
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ste,pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
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ste,config = <&in_pu>;
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};
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};
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i2c3_sleep_mode: i2c_sleep {
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sleep_cfg1 {
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ste,pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
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ste,config = <&slpm_in_wkup_pdis>;
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};
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};
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};
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/*
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* Activating I2C4 will conflict with UART1 about the same pins so do not
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* enable I2C4 and UART1 at the same time.
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*/
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i2c4 {
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i2c4_default_mode: i2c_default {
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default_mux {
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ste,function = "i2c4";
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ste,pins = "i2c4_b_1";
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};
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default_cfg1 {
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ste,pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
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ste,config = <&in_pu>;
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};
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};
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i2c4_sleep_mode: i2c_sleep {
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sleep_cfg1 {
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ste,pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
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ste,config = <&slpm_in_wkup_pdis>;
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};
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};
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};
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/* Settings for all SPI default and sleep states */
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spi2 {
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spi2_default_mode: spi_default {
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default_mux {
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ste,function = "spi2";
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ste,pins = "spi2_oc1_2";
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};
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default_cfg1 {
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ste,pins = "GPIO216_AG12"; /* FRM */
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ste,config = <&gpio_out_hi>;
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};
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default_cfg2 {
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ste,pins = "GPIO218_AH11"; /* RXD */
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ste,config = <&in_pd>;
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};
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default_cfg3 {
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ste,pins =
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"GPIO215_AH13", /* TXD */
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"GPIO217_AH12"; /* CLK */
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ste,config = <&out_lo>;
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};
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};
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spi2_idle_mode: spi_idle {
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/*
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* The idle mode is basically sleep mode sans wakeups. Also
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* note that we have muxes the pins off the function here
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* as we do not state any muxing.
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*/
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idle_cfg1 {
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ste,pins = "GPIO218_AH11"; /* RXD */
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ste,config = <&slpm_in_pdis>;
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};
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idle_cfg2 {
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ste,pins = "GPIO215_AH13"; /* TXD */
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ste,config = <&slpm_out_lo_pdis>;
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};
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idle_cfg3 {
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ste,pins = "GPIO217_AH12"; /* CLK */
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ste,config = <&slpm_pdis>;
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};
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};
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spi2_sleep_mode: spi_sleep {
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sleep_cfg1 {
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ste,pins =
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"GPIO216_AG12", /* FRM */
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"GPIO218_AH11"; /* RXD */
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ste,config = <&slpm_in_wkup_pdis>;
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};
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sleep_cfg2 {
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ste,pins = "GPIO215_AH13"; /* TXD */
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ste,config = <&slpm_out_lo_wkup_pdis>;
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};
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sleep_cfg3 {
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ste,pins = "GPIO217_AH12"; /* CLK */
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ste,config = <&slpm_wkup_pdis>;
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};
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};
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};
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/* Settings for all MMC/SD/SDIO default and sleep states */
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sdi0 {
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/* This is the external SD card slot, 4 bits wide */
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sdi0_default_mode: sdi0_default {
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default_mux {
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ste,function = "mc0";
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ste,pins = "mc0_a_1";
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};
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default_cfg1 {
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ste,pins =
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"GPIO18_AC2", /* CMDDIR */
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"GPIO19_AC1", /* DAT0DIR */
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"GPIO20_AB4"; /* DAT2DIR */
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ste,config = <&out_hi>;
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};
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default_cfg2 {
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ste,pins = "GPIO22_AA3"; /* FBCLK */
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ste,config = <&in_nopull>;
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};
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default_cfg3 {
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ste,pins = "GPIO23_AA4"; /* CLK */
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ste,config = <&out_lo>;
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};
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default_cfg4 {
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ste,pins =
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"GPIO24_AB2", /* CMD */
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"GPIO25_Y4", /* DAT0 */
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"GPIO26_Y2", /* DAT1 */
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"GPIO27_AA2", /* DAT2 */
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"GPIO28_AA1"; /* DAT3 */
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ste,config = <&in_pu>;
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};
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};
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sdi0_sleep_mode: sdi0_sleep {
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sleep_cfg1 {
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ste,pins =
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"GPIO18_AC2", /* CMDDIR */
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"GPIO19_AC1", /* DAT0DIR */
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"GPIO20_AB4"; /* DAT2DIR */
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ste,config = <&slpm_out_hi_wkup_pdis>;
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};
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sleep_cfg2 {
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ste,pins =
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"GPIO22_AA3", /* FBCLK */
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"GPIO24_AB2", /* CMD */
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"GPIO25_Y4", /* DAT0 */
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"GPIO26_Y2", /* DAT1 */
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"GPIO27_AA2", /* DAT2 */
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"GPIO28_AA1"; /* DAT3 */
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ste,config = <&slpm_in_wkup_pdis>;
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};
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sleep_cfg3 {
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ste,pins = "GPIO23_AA4"; /* CLK */
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ste,config = <&slpm_out_lo_wkup_pdis>;
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};
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};
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};
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sdi1 {
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/* This is the WLAN SDIO 4 bits wide */
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sdi1_default_mode: sdi1_default {
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default_mux {
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ste,function = "mc1";
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ste,pins = "mc1_a_1";
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};
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default_cfg1 {
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ste,pins = "GPIO208_AH16"; /* CLK */
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ste,config = <&out_lo>;
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};
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default_cfg2 {
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ste,pins = "GPIO209_AG15"; /* FBCLK */
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ste,config = <&in_nopull>;
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};
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default_cfg3 {
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ste,pins =
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"GPIO210_AJ15", /* CMD */
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"GPIO211_AG14", /* DAT0 */
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"GPIO212_AF13", /* DAT1 */
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"GPIO213_AG13", /* DAT2 */
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"GPIO214_AH15"; /* DAT3 */
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ste,config = <&in_pu>;
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};
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};
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sdi1_sleep_mode: sdi1_sleep {
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sleep_cfg1 {
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ste,pins = "GPIO208_AH16"; /* CLK */
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ste,config = <&slpm_out_lo_wkup_pdis>;
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};
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sleep_cfg2 {
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ste,pins =
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"GPIO209_AG15", /* FBCLK */
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"GPIO210_AJ15", /* CMD */
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"GPIO211_AG14", /* DAT0 */
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"GPIO212_AF13", /* DAT1 */
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"GPIO213_AG13", /* DAT2 */
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"GPIO214_AH15"; /* DAT3 */
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ste,config = <&slpm_in_wkup_pdis>;
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};
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};
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};
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|
sdi2 {
|
||
|
|
/* This is the eMMC 8 bits wide, usually PoP eMMC */
|
||
|
|
sdi2_default_mode: sdi2_default {
|
||
|
|
default_mux {
|
||
|
|
ste,function = "mc2";
|
||
|
|
ste,pins = "mc2_a_1";
|
||
|
|
};
|
||
|
|
default_cfg1 {
|
||
|
|
ste,pins = "GPIO128_A5"; /* CLK */
|
||
|
|
ste,config = <&out_lo>;
|
||
|
|
};
|
||
|
|
default_cfg2 {
|
||
|
|
ste,pins = "GPIO130_C8"; /* FBCLK */
|
||
|
|
ste,config = <&in_nopull>;
|
||
|
|
};
|
||
|
|
default_cfg3 {
|
||
|
|
ste,pins =
|
||
|
|
"GPIO129_B4", /* CMD */
|
||
|
|
"GPIO131_A12", /* DAT0 */
|
||
|
|
"GPIO132_C10", /* DAT1 */
|
||
|
|
"GPIO133_B10", /* DAT2 */
|
||
|
|
"GPIO134_B9", /* DAT3 */
|
||
|
|
"GPIO135_A9", /* DAT4 */
|
||
|
|
"GPIO136_C7", /* DAT5 */
|
||
|
|
"GPIO137_A7", /* DAT6 */
|
||
|
|
"GPIO138_C5"; /* DAT7 */
|
||
|
|
ste,config = <&in_pu>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
sdi2_sleep_mode: sdi2_sleep {
|
||
|
|
sleep_cfg1 {
|
||
|
|
ste,pins = "GPIO128_A5"; /* CLK */
|
||
|
|
ste,config = <&out_lo_wkup_pdis>;
|
||
|
|
};
|
||
|
|
sleep_cfg2 {
|
||
|
|
ste,pins =
|
||
|
|
"GPIO130_C8", /* FBCLK */
|
||
|
|
"GPIO129_B4"; /* CMD */
|
||
|
|
ste,config = <&in_wkup_pdis_en>;
|
||
|
|
};
|
||
|
|
sleep_cfg3 {
|
||
|
|
ste,pins =
|
||
|
|
"GPIO131_A12", /* DAT0 */
|
||
|
|
"GPIO132_C10", /* DAT1 */
|
||
|
|
"GPIO133_B10", /* DAT2 */
|
||
|
|
"GPIO134_B9", /* DAT3 */
|
||
|
|
"GPIO135_A9", /* DAT4 */
|
||
|
|
"GPIO136_C7", /* DAT5 */
|
||
|
|
"GPIO137_A7", /* DAT6 */
|
||
|
|
"GPIO138_C5"; /* DAT7 */
|
||
|
|
ste,config = <&in_wkup_pdis>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
sdi4 {
|
||
|
|
/* This is the eMMC 8 bits wide, usually PCB-mounted eMMC */
|
||
|
|
sdi4_default_mode: sdi4_default {
|
||
|
|
default_mux {
|
||
|
|
ste,function = "mc4";
|
||
|
|
ste,pins = "mc4_a_1";
|
||
|
|
};
|
||
|
|
default_cfg1 {
|
||
|
|
ste,pins = "GPIO203_AE23"; /* CLK */
|
||
|
|
ste,config = <&out_lo>;
|
||
|
|
};
|
||
|
|
default_cfg2 {
|
||
|
|
ste,pins = "GPIO202_AF25"; /* FBCLK */
|
||
|
|
ste,config = <&in_nopull>;
|
||
|
|
};
|
||
|
|
default_cfg3 {
|
||
|
|
ste,pins =
|
||
|
|
"GPIO201_AF24", /* CMD */
|
||
|
|
"GPIO200_AH26", /* DAT0 */
|
||
|
|
"GPIO199_AH23", /* DAT1 */
|
||
|
|
"GPIO198_AG25", /* DAT2 */
|
||
|
|
"GPIO197_AH24", /* DAT3 */
|
||
|
|
"GPIO207_AJ23", /* DAT4 */
|
||
|
|
"GPIO206_AG24", /* DAT5 */
|
||
|
|
"GPIO205_AG23", /* DAT6 */
|
||
|
|
"GPIO204_AF23"; /* DAT7 */
|
||
|
|
ste,config = <&in_pu>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
sdi4_sleep_mode: sdi4_sleep {
|
||
|
|
sleep_cfg1 {
|
||
|
|
ste,pins = "GPIO203_AE23"; /* CLK */
|
||
|
|
ste,config = <&out_lo_wkup_pdis>;
|
||
|
|
};
|
||
|
|
sleep_cfg2 {
|
||
|
|
ste,pins =
|
||
|
|
"GPIO202_AF25", /* FBCLK */
|
||
|
|
"GPIO201_AF24", /* CMD */
|
||
|
|
"GPIO200_AH26", /* DAT0 */
|
||
|
|
"GPIO199_AH23", /* DAT1 */
|
||
|
|
"GPIO198_AG25", /* DAT2 */
|
||
|
|
"GPIO197_AH24", /* DAT3 */
|
||
|
|
"GPIO207_AJ23", /* DAT4 */
|
||
|
|
"GPIO206_AG24", /* DAT5 */
|
||
|
|
"GPIO205_AG23", /* DAT6 */
|
||
|
|
"GPIO204_AF23"; /* DAT7 */
|
||
|
|
ste,config = <&slpm_in_wkup_pdis>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Multi-rate serial ports (MSPs) - MSP3 output is internal and
|
||
|
|
* cannot be muxed onto any pins.
|
||
|
|
*/
|
||
|
|
msp0 {
|
||
|
|
msp0_default_mode: msp0_default {
|
||
|
|
default_msp0_mux {
|
||
|
|
ste,function = "msp0";
|
||
|
|
ste,pins = "msp0txrx_a_1", "msp0tfstck_a_1";
|
||
|
|
};
|
||
|
|
default_msp0_cfg {
|
||
|
|
ste,pins =
|
||
|
|
"GPIO12_AC4", /* TXD */
|
||
|
|
"GPIO15_AC3", /* RXD */
|
||
|
|
"GPIO13_AF3", /* TFS */
|
||
|
|
"GPIO14_AE3"; /* TCK */
|
||
|
|
ste,config = <&in_nopull>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
msp1 {
|
||
|
|
msp1_default_mode: msp1_default {
|
||
|
|
default_mux {
|
||
|
|
ste,function = "msp1";
|
||
|
|
ste,pins = "msp1txrx_a_1", "msp1_a_1";
|
||
|
|
};
|
||
|
|
default_cfg1 {
|
||
|
|
ste,pins = "GPIO33_AF2";
|
||
|
|
ste,config = <&out_lo>;
|
||
|
|
};
|
||
|
|
default_cfg2 {
|
||
|
|
ste,pins =
|
||
|
|
"GPIO34_AE1",
|
||
|
|
"GPIO35_AE2",
|
||
|
|
"GPIO36_AG2";
|
||
|
|
ste,config = <&in_nopull>;
|
||
|
|
};
|
||
|
|
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
msp2 {
|
||
|
|
msp2_default_mode: msp2_default {
|
||
|
|
/* MSP2 usually used for HDMI audio */
|
||
|
|
default_mux {
|
||
|
|
ste,function = "msp2";
|
||
|
|
ste,pins = "msp2_a_1";
|
||
|
|
};
|
||
|
|
default_cfg1 {
|
||
|
|
ste,pins =
|
||
|
|
"GPIO193_AH27", /* TXD */
|
||
|
|
"GPIO194_AF27", /* TCK */
|
||
|
|
"GPIO195_AG28"; /* TFS */
|
||
|
|
ste,config = <&in_pd>;
|
||
|
|
};
|
||
|
|
default_cfg2 {
|
||
|
|
ste,pins = "GPIO196_AG26"; /* RXD */
|
||
|
|
ste,config = <&out_lo>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
|
||
|
|
musb {
|
||
|
|
musb_default_mode: musb_default {
|
||
|
|
default_mux {
|
||
|
|
ste,function = "usb";
|
||
|
|
ste,pins = "usb_a_1";
|
||
|
|
};
|
||
|
|
default_cfg1 {
|
||
|
|
ste,pins =
|
||
|
|
"GPIO256_AF28", /* NXT */
|
||
|
|
"GPIO258_AD29", /* XCLK */
|
||
|
|
"GPIO259_AC29", /* DIR */
|
||
|
|
"GPIO260_AD28", /* DAT7 */
|
||
|
|
"GPIO261_AD26", /* DAT6 */
|
||
|
|
"GPIO262_AE26", /* DAT5 */
|
||
|
|
"GPIO263_AG29", /* DAT4 */
|
||
|
|
"GPIO264_AE27", /* DAT3 */
|
||
|
|
"GPIO265_AD27", /* DAT2 */
|
||
|
|
"GPIO266_AC28", /* DAT1 */
|
||
|
|
"GPIO267_AC27"; /* DAT0 */
|
||
|
|
ste,config = <&in_nopull>;
|
||
|
|
};
|
||
|
|
default_cfg2 {
|
||
|
|
ste,pins = "GPIO257_AE29"; /* STP */
|
||
|
|
ste,config = <&out_hi>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
musb_sleep_mode: musb_sleep {
|
||
|
|
sleep_cfg1 {
|
||
|
|
ste,pins =
|
||
|
|
"GPIO256_AF28", /* NXT */
|
||
|
|
"GPIO258_AD29", /* XCLK */
|
||
|
|
"GPIO259_AC29"; /* DIR */
|
||
|
|
ste,config = <&slpm_wkup_pdis_en>;
|
||
|
|
};
|
||
|
|
sleep_cfg2 {
|
||
|
|
ste,pins = "GPIO257_AE29"; /* STP */
|
||
|
|
ste,config = <&slpm_out_hi_wkup_pdis>;
|
||
|
|
};
|
||
|
|
sleep_cfg3 {
|
||
|
|
ste,pins =
|
||
|
|
"GPIO260_AD28", /* DAT7 */
|
||
|
|
"GPIO261_AD26", /* DAT6 */
|
||
|
|
"GPIO262_AE26", /* DAT5 */
|
||
|
|
"GPIO263_AG29", /* DAT4 */
|
||
|
|
"GPIO264_AE27", /* DAT3 */
|
||
|
|
"GPIO265_AD27", /* DAT2 */
|
||
|
|
"GPIO266_AC28", /* DAT1 */
|
||
|
|
"GPIO267_AC27"; /* DAT0 */
|
||
|
|
ste,config = <&slpm_in_wkup_pdis_en>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
mcde {
|
||
|
|
lcd_default_mode: lcd_default {
|
||
|
|
default_mux {
|
||
|
|
/* Mux in VSI0 and all the data lines */
|
||
|
|
ste,function = "lcd";
|
||
|
|
ste,pins =
|
||
|
|
"lcdvsi0_a_1", /* VSI0 for LCD */
|
||
|
|
"lcd_d0_d7_a_1", /* Data lines */
|
||
|
|
"lcd_d8_d11_a_1", /* TV-out */
|
||
|
|
"lcdaclk_b_1", /* Clock line for TV-out */
|
||
|
|
"lcdvsi1_a_1"; /* VSI1 for HDMI */
|
||
|
|
};
|
||
|
|
default_cfg1 {
|
||
|
|
ste,pins =
|
||
|
|
"GPIO68_E1", /* VSI0 */
|
||
|
|
"GPIO69_E2"; /* VSI1 */
|
||
|
|
ste,config = <&in_pu>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
lcd_sleep_mode: lcd_sleep {
|
||
|
|
sleep_cfg1 {
|
||
|
|
ste,pins = "GPIO69_E2"; /* VSI1 */
|
||
|
|
ste,config = <&slpm_in_wkup_pdis>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
ske {
|
||
|
|
/* SKE keys on position 2 in an 8x8 matrix */
|
||
|
|
ske_kpa2_default_mode: ske_kpa2_default {
|
||
|
|
default_mux {
|
||
|
|
ste,function = "kp";
|
||
|
|
ste,pins = "kp_a_2";
|
||
|
|
};
|
||
|
|
default_cfg1 {
|
||
|
|
ste,pins =
|
||
|
|
"GPIO153_B17", /* I7 */
|
||
|
|
"GPIO154_C16", /* I6 */
|
||
|
|
"GPIO155_C19", /* I5 */
|
||
|
|
"GPIO156_C17", /* I4 */
|
||
|
|
"GPIO161_D21", /* I3 */
|
||
|
|
"GPIO162_D20", /* I2 */
|
||
|
|
"GPIO163_C20", /* I1 */
|
||
|
|
"GPIO164_B21"; /* I0 */
|
||
|
|
ste,config = <&in_pd>;
|
||
|
|
};
|
||
|
|
default_cfg2 {
|
||
|
|
ste,pins =
|
||
|
|
"GPIO157_A18", /* O7 */
|
||
|
|
"GPIO158_C18", /* O6 */
|
||
|
|
"GPIO159_B19", /* O5 */
|
||
|
|
"GPIO160_B20", /* O4 */
|
||
|
|
"GPIO165_C21", /* O3 */
|
||
|
|
"GPIO166_A22", /* O2 */
|
||
|
|
"GPIO167_B24", /* O1 */
|
||
|
|
"GPIO168_C22"; /* O0 */
|
||
|
|
ste,config = <&out_lo>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
ske_kpa2_sleep_mode: ske_kpa2_sleep {
|
||
|
|
sleep_cfg1 {
|
||
|
|
ste,pins =
|
||
|
|
"GPIO153_B17", /* I7 */
|
||
|
|
"GPIO154_C16", /* I6 */
|
||
|
|
"GPIO155_C19", /* I5 */
|
||
|
|
"GPIO156_C17", /* I4 */
|
||
|
|
"GPIO161_D21", /* I3 */
|
||
|
|
"GPIO162_D20", /* I2 */
|
||
|
|
"GPIO163_C20", /* I1 */
|
||
|
|
"GPIO164_B21"; /* I0 */
|
||
|
|
ste,config = <&slpm_in_pu_wkup_pdis_en>;
|
||
|
|
};
|
||
|
|
sleep_cfg2 {
|
||
|
|
ste,pins =
|
||
|
|
"GPIO157_A18", /* O7 */
|
||
|
|
"GPIO158_C18", /* O6 */
|
||
|
|
"GPIO159_B19", /* O5 */
|
||
|
|
"GPIO160_B20", /* O4 */
|
||
|
|
"GPIO165_C21", /* O3 */
|
||
|
|
"GPIO166_A22", /* O2 */
|
||
|
|
"GPIO167_B24", /* O1 */
|
||
|
|
"GPIO168_C22"; /* O0 */
|
||
|
|
ste,config = <&slpm_out_lo_pdis>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
/*
|
||
|
|
* SKE keys on position 1 and "other C1" combi giving
|
||
|
|
* six rows of six keys.
|
||
|
|
*/
|
||
|
|
ske_kpaoc1_default_mode: ske_kpaoc1_default {
|
||
|
|
default_mux {
|
||
|
|
ste,function = "kp";
|
||
|
|
ste,pins = "kp_a_1", "kp_oc1_1";
|
||
|
|
};
|
||
|
|
default_cfg1 {
|
||
|
|
ste,pins =
|
||
|
|
"GPIO91_B6", /* KP_O0 */
|
||
|
|
"GPIO90_A3", /* KP_O1 */
|
||
|
|
"GPIO87_B3", /* KP_O2 */
|
||
|
|
"GPIO86_C6", /* KP_O3 */
|
||
|
|
"GPIO96_D8", /* KP_O6 */
|
||
|
|
"GPIO94_D7"; /* KP_O7 */
|
||
|
|
ste,config = <&out_lo>;
|
||
|
|
};
|
||
|
|
default_cfg2 {
|
||
|
|
ste,pins =
|
||
|
|
"GPIO93_B7", /* KP_I0 */
|
||
|
|
"GPIO92_D6", /* KP_I1 */
|
||
|
|
"GPIO89_E6", /* KP_I2 */
|
||
|
|
"GPIO88_C4", /* KP_I3 */
|
||
|
|
"GPIO97_D9", /* KP_I6 */
|
||
|
|
"GPIO95_E8"; /* KP_I7 */
|
||
|
|
ste,config = <&in_pu>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
wlan {
|
||
|
|
wlan_default_mode: wlan_default {
|
||
|
|
/*
|
||
|
|
* Activate this mode with the WLAN chip.
|
||
|
|
* These are plain GPIO pins used by WLAN
|
||
|
|
*/
|
||
|
|
default_cfg1 {
|
||
|
|
ste,pins =
|
||
|
|
"GPIO226_AF8", /* WLAN_PMU_EN */
|
||
|
|
"GPIO85_D5"; /* WLAN_ENA */
|
||
|
|
ste,config = <&gpio_out_lo>;
|
||
|
|
};
|
||
|
|
default_cfg2 {
|
||
|
|
ste,pins = "GPIO4_AH6"; /* WLAN_IRQ on UART1 */
|
||
|
|
ste,config = <&gpio_in_pu>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|