289 lines
6.6 KiB
Plaintext
289 lines
6.6 KiB
Plaintext
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/*
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* Copyright 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
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* Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>, Pengutronix
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include "imx53.dtsi"
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/ {
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model = "TQ TQMa53";
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compatible = "tq,tqma53", "fsl,imx53";
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memory {
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reg = <0x70000000 0x40000000>; /* Up to 1GiB */
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};
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regulators {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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reg_3p3v: regulator@0 {
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compatible = "regulator-fixed";
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reg = <0>;
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regulator-name = "3P3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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};
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};
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&esdhc2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_esdhc2>,
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<&pinctrl_esdhc2_cdwp>;
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vmmc-supply = <®_3p3v>;
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wp-gpios = <&gpio1 2 0>;
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cd-gpios = <&gpio1 4 0>;
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status = "disabled";
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};
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&uart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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status = "disabled";
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};
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&ecspi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi1>;
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fsl,spi-num-chipselects = <4>;
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cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>,
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<&gpio3 24 0>, <&gpio3 25 0>;
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status = "disabled";
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};
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&esdhc3 { /* EMMC */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_esdhc3>;
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vmmc-supply = <®_3p3v>;
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non-removable;
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bus-width = <8>;
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status = "okay";
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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imx53-tqma53 {
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pinctrl_hog: hoggrp {
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fsl,pins = <
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MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 /* SSI_MCLK */
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MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000 /* LCD_BLT_EN */
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MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000 /* LCD_RESET */
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MX53_PAD_PATA_DATA5__GPIO2_5 0x80000000 /* LCD_POWER */
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MX53_PAD_PATA_DATA6__GPIO2_6 0x80000000 /* PMIC_INT */
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MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 /* CSI_RST */
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MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 /* CSI_PWDN */
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MX53_PAD_GPIO_19__GPIO4_5 0x80000000 /* #SYSTEM_DOWN */
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MX53_PAD_GPIO_3__GPIO1_3 0x80000000
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MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 /* #PHY_RESET */
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MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000 /* LCD_CONTRAST */
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>;
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};
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pinctrl_audmux: audmuxgrp {
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fsl,pins = <
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MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
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MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
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MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
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MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
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>;
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};
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pinctrl_can1: can1grp {
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fsl,pins = <
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MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000
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MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000
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>;
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};
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pinctrl_can2: can2grp {
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fsl,pins = <
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MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
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MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
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>;
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};
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pinctrl_cspi: cspigrp {
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fsl,pins = <
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MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5
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MX53_PAD_SD1_CMD__CSPI_MOSI 0x1d5
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MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5
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>;
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};
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pinctrl_ecspi1: ecspi1grp {
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fsl,pins = <
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MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
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MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
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MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
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>;
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};
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pinctrl_esdhc2: esdhc2grp {
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fsl,pins = <
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MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
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MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
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MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
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MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
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MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
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MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
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>;
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};
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pinctrl_esdhc2_cdwp: esdhc2cdwp {
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fsl,pins = <
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MX53_PAD_GPIO_4__GPIO1_4 0x80000000 /* SD2_CD */
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MX53_PAD_GPIO_2__GPIO1_2 0x80000000 /* SD2_WP */
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>;
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};
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pinctrl_esdhc3: esdhc3grp {
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fsl,pins = <
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MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
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MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
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MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
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MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
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MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
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MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
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MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
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MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
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MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
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MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
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>;
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};
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pinctrl_fec: fecgrp {
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fsl,pins = <
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MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
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MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
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MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
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MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
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MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
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MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
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MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
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MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
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MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
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MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
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MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
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>;
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};
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pinctrl_i2c3: i2c3grp {
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fsl,pins = <
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MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
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MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
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MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
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>;
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};
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pinctrl_uart2: uart2grp {
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fsl,pins = <
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MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
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MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
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>;
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};
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pinctrl_uart3: uart3grp {
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fsl,pins = <
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MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
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MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
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>;
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};
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};
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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fsl,uart-has-rtscts;
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status = "disabled";
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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status = "disabled";
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};
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&can1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_can1>;
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status = "disabled";
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};
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&can2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_can2>;
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status = "disabled";
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};
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&i2c3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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status = "disabled";
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};
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&cspi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_cspi>;
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fsl,spi-num-chipselects = <3>;
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cs-gpios = <&gpio1 18 0>, <&gpio1 19 0>,
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<&gpio1 21 0>;
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status = "disabled";
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};
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&i2c2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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pmic: mc34708@8 {
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compatible = "fsl,mc34708";
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reg = <0x8>;
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fsl,mc13xxx-uses-rtc;
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interrupt-parent = <&gpio2>;
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interrupts = <6 4>; /* PATA_DATA6, active high */
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};
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sensor1: lm75@48 {
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compatible = "lm75";
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reg = <0x48>;
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};
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eeprom: 24c64@50 {
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compatible = "at,24c64";
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pagesize = <32>;
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reg = <0x50>;
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};
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec>;
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phy-mode = "rmii";
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status = "disabled";
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};
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