M7350/kernel/arch/arm/boot/dts/bcm2835.dtsi

/include/ "skeleton.dtsi"

/ {
	compatible = "brcm,bcm2835";
	model = "BCM2835";
	interrupt-parent = <&intc>;

	chosen {
		bootargs = "earlyprintk console=ttyAMA0";
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x7e000000 0x20000000 0x02000000>;

		timer@7e003000 {
			compatible = "brcm,bcm2835-system-timer";
			reg = <0x7e003000 0x1000>;
			interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
			clock-frequency = <1000000>;
		};

		dma: dma@7e007000 {
			compatible = "brcm,bcm2835-dma";
			reg = <0x7e007000 0xf00>;
			interrupts = <1 16>,
				     <1 17>,
				     <1 18>,
				     <1 19>,
				     <1 20>,
				     <1 21>,
				     <1 22>,
				     <1 23>,
				     <1 24>,
				     <1 25>,
				     <1 26>,
				     <1 27>,
				     <1 28>;

			#dma-cells = <1>;
			brcm,dma-channel-mask = <0x7f35>;
		};

		intc: interrupt-controller@7e00b200 {
			compatible = "brcm,bcm2835-armctrl-ic";
			reg = <0x7e00b200 0x200>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		watchdog@7e100000 {
			compatible = "brcm,bcm2835-pm-wdt";
			reg = <0x7e100000 0x28>;
		};

		rng@7e104000 {
			compatible = "brcm,bcm2835-rng";
			reg = <0x7e104000 0x10>;
		};

		gpio: gpio@7e200000 {
			compatible = "brcm,bcm2835-gpio";
			reg = <0x7e200000 0xb4>;
			/*
			 * The GPIO IP block is designed for 3 banks of GPIOs.
			 * Each bank has a GPIO interrupt for itself.
			 * There is an overall "any bank" interrupt.
			 * In order, these are GIC interrupts 17, 18, 19, 20.
			 * Since the BCM2835 only has 2 banks, the 2nd bank
			 * interrupt output appears to be mirrored onto the
			 * 3rd bank's interrupt signal.
			 * So, a bank0 interrupt shows up on 17, 20, and
			 * a bank1 interrupt shows up on 18, 19, 20!
			 */
			interrupts = <2 17>, <2 18>, <2 19>, <2 20>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		uart@7e201000 {
			compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
			reg = <0x7e201000 0x1000>;
			interrupts = <2 25>;
			clock-frequency = <3000000>;
			arm,primecell-periphid = <0x00241011>;
		};

		i2s: i2s@7e203000 {
			compatible = "brcm,bcm2835-i2s";
			reg = <0x7e203000 0x20>,
			      <0x7e101098 0x02>;

			dmas = <&dma 2>,
			       <&dma 3>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		spi: spi@7e204000 {
			compatible = "brcm,bcm2835-spi";
			reg = <0x7e204000 0x1000>;
			interrupts = <2 22>;
			clocks = <&clk_spi>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c0: i2c@20205000 {
			compatible = "brcm,bcm2835-i2c";
			reg = <0x7e205000 0x1000>;
			interrupts = <2 21>;
			clocks = <&clk_i2c>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		sdhci: sdhci@7e300000 {
			compatible = "brcm,bcm2835-sdhci";
			reg = <0x7e300000 0x100>;
			interrupts = <2 30>;
			clocks = <&clk_mmc>;
			status = "disabled";
		};

		i2c1: i2c@7e804000 {
			compatible = "brcm,bcm2835-i2c";
			reg = <0x7e804000 0x1000>;
			interrupts = <2 21>;
			clocks = <&clk_i2c>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		usb@7e980000 {
			compatible = "brcm,bcm2835-usb";
			reg = <0x7e980000 0x10000>;
			interrupts = <1 9>;
		};

		arm-pmu {
			compatible = "arm,arm1176-pmu";
		};
	};

	clocks {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		clk_mmc: clock@0 {
			compatible = "fixed-clock";
			reg = <0>;
			#clock-cells = <0>;
			clock-output-names = "mmc";
			clock-frequency = <100000000>;
		};

		clk_i2c: clock@1 {
			compatible = "fixed-clock";
			reg = <1>;
			#clock-cells = <0>;
			clock-output-names = "i2c";
			clock-frequency = <250000000>;
		};

		clk_spi: clock@2 {
			compatible = "fixed-clock";
			reg = <2>;
			#clock-cells = <0>;
			clock-output-names = "spi";
			clock-frequency = <250000000>;
		};
	};
};