43 lines
1.5 KiB
Plaintext
43 lines
1.5 KiB
Plaintext
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Qualcomm CPU clock Ramp Controller
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The root clock generator could have the ramp controller in built.
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Ramp control will allow programming the sequence ID for pulse swallowing,
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enable sequence and for linking sequence IDs.
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This will use the cpu clock device node.
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Required properties:
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- reg: Pairs of physical base addresses and region sizes of
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memory mapped registers.
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- reg-names: Names of the bases for the above registers. Expected
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bases are:
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"rcgwr-cX-base" (X: 0 or 1 based on the number of
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clusters)
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- qcom,num-clusters: Number of clusters which support RCGwR.
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Optional Properties:
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- qcom,lmh-sid-cX: List of LMH SID offset and value to be programmed for
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each cluster (X: 0 or 1)
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- qcom,link-sid-cX: List of Link SID offset and value to be programmed for
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each cluster (X: 0 or 1)
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- qcom,dfs-sid-cX: List of DFS SID offset and value to be programmed for
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each cluster (X: 0 or 1)
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- qcom,ramp-dis-cX: Boolean property to disable ramp down for each cluster
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(X: 0 or 1)
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Example:
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clock_cpu: qcom,cpu-clock@b016000 {
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compatible = "qcom,cpu-clock";
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qcom,num-clusters = <2>;
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qcom,lmh-sid-c0 = < 0x30 0x077706db>,
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< 0x34 0x05550249>,
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< 0x38 0x00000111>;
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qcom,lmh-sid-c1 = < 0x30 0x077706db>,
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< 0x34 0x05550249>,
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< 0x38 0x00000111>;
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reg = <0xb114000 0x68>,
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<0xb014000 0x68>;
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reg-names = "rcgwr-c0-base", "rcgwr-c1-base";
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#clock-cells = <1>;
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};
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