2024-09-09 08:52:07 +00:00
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/*
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* Copyright (c) 2010 Broadcom Corporation
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
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* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
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* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _BRCM_NICPCI_H_
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#define _BRCM_NICPCI_H_
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#include "types.h"
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/* PCI configuration address space size */
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#define PCI_SZPCR 256
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/* Brcm PCI configuration registers */
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/* backplane address space accessed by BAR0 */
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#define PCI_BAR0_WIN 0x80
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/* sprom property control */
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#define PCI_SPROM_CONTROL 0x88
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/* mask of PCI and other cores interrupts */
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#define PCI_INT_MASK 0x94
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/* backplane core interrupt mask bits offset */
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#define PCI_SBIM_SHIFT 8
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/* backplane address space accessed by second 4KB of BAR0 */
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#define PCI_BAR0_WIN2 0xac
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/* pci config space gpio input (>=rev3) */
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#define PCI_GPIO_IN 0xb0
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/* pci config space gpio output (>=rev3) */
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#define PCI_GPIO_OUT 0xb4
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/* pci config space gpio output enable (>=rev3) */
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#define PCI_GPIO_OUTEN 0xb8
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/* bar0 + 4K accesses external sprom */
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#define PCI_BAR0_SPROM_OFFSET (4 * 1024)
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/* bar0 + 6K accesses pci core registers */
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#define PCI_BAR0_PCIREGS_OFFSET (6 * 1024)
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/*
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* pci core SB registers are at the end of the
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* 8KB window, so their address is the "regular"
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* address plus 4K
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*/
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#define PCI_BAR0_PCISBR_OFFSET (4 * 1024)
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/* bar0 window size Match with corerev 13 */
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#define PCI_BAR0_WINSZ (16 * 1024)
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/* On pci corerev >= 13 and all pcie, the bar0 is now 16KB and it maps: */
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/* bar0 + 8K accesses pci/pcie core registers */
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#define PCI_16KB0_PCIREGS_OFFSET (8 * 1024)
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/* bar0 + 12K accesses chipc core registers */
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#define PCI_16KB0_CCREGS_OFFSET (12 * 1024)
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struct sbpciregs;
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struct sbpcieregs;
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extern struct pcicore_info *pcicore_init(struct si_pub *sih,
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2024-09-09 08:57:42 +00:00
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struct pci_dev *pdev,
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void __iomem *regs);
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2024-09-09 08:52:07 +00:00
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extern void pcicore_deinit(struct pcicore_info *pch);
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extern void pcicore_attach(struct pcicore_info *pch, int state);
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extern void pcicore_hwup(struct pcicore_info *pch);
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extern void pcicore_up(struct pcicore_info *pch, int state);
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extern void pcicore_sleep(struct pcicore_info *pch);
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extern void pcicore_down(struct pcicore_info *pch, int state);
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extern u8 pcicore_find_pci_capability(struct pci_dev *dev, u8 req_cap_id,
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unsigned char *buf, u32 *buflen);
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2024-09-09 08:57:42 +00:00
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extern void pcicore_fixcfg_pci(struct pcicore_info *pch,
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struct sbpciregs __iomem *pciregs);
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extern void pcicore_fixcfg_pcie(struct pcicore_info *pch,
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struct sbpcieregs __iomem *pciregs);
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extern void pcicore_pci_setup(struct pcicore_info *pch,
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struct sbpciregs __iomem *pciregs);
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2024-09-09 08:52:07 +00:00
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#endif /* _BRCM_NICPCI_H_ */
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