2024-09-09 08:52:07 +00:00
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/*
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* Copyright (c) 2008-2011 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include "hw.h"
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#include "ar9003_mac.h"
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#include "ar9003_2p2_initvals.h"
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#include "ar9485_initvals.h"
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#include "ar9340_initvals.h"
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#include "ar9330_1p1_initvals.h"
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#include "ar9330_1p2_initvals.h"
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#include "ar9580_1p0_initvals.h"
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2024-09-09 08:57:42 +00:00
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#include "ar9462_1p0_initvals.h"
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2024-09-09 08:52:07 +00:00
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#include "ar9462_2p0_initvals.h"
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/* General hardware code for the AR9003 hadware family */
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/*
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* The AR9003 family uses a new INI format (pre, core, post
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* arrays per subsystem). This provides support for the
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* AR9003 2.2 chipsets.
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*/
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static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
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{
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#define PCIE_PLL_ON_CREQ_DIS_L1_2P0 \
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ar9462_pciephy_pll_on_clkreq_disable_L1_2p0
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#define AR9462_BB_CTX_COEFJ(x) \
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ar9462_##x##_baseband_core_txfir_coeff_japan_2484
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#define AR9462_BBC_TXIFR_COEFFJ \
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ar9462_2p0_baseband_core_txfir_coeff_japan_2484
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if (AR_SREV_9330_11(ah)) {
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/* mac */
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
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ar9331_1p1_mac_core,
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ARRAY_SIZE(ar9331_1p1_mac_core), 2);
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
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ar9331_1p1_mac_postamble,
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ARRAY_SIZE(ar9331_1p1_mac_postamble), 5);
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/* bb */
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
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ar9331_1p1_baseband_core,
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ARRAY_SIZE(ar9331_1p1_baseband_core), 2);
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
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ar9331_1p1_baseband_postamble,
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ARRAY_SIZE(ar9331_1p1_baseband_postamble), 5);
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/* radio */
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
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ar9331_1p1_radio_core,
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ARRAY_SIZE(ar9331_1p1_radio_core), 2);
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], NULL, 0, 0);
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/* soc */
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
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ar9331_1p1_soc_preamble,
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ARRAY_SIZE(ar9331_1p1_soc_preamble), 2);
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
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ar9331_1p1_soc_postamble,
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ARRAY_SIZE(ar9331_1p1_soc_postamble), 2);
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/* rx/tx gain */
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INIT_INI_ARRAY(&ah->iniModesRxGain,
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ar9331_common_rx_gain_1p1,
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ARRAY_SIZE(ar9331_common_rx_gain_1p1), 2);
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9331_modes_lowest_ob_db_tx_gain_1p1,
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ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1),
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5);
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/* additional clock settings */
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if (ah->is_clk_25mhz)
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2024-09-09 08:57:42 +00:00
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INIT_INI_ARRAY(&ah->iniModesAdditional,
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2024-09-09 08:52:07 +00:00
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ar9331_1p1_xtal_25M,
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ARRAY_SIZE(ar9331_1p1_xtal_25M), 2);
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else
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2024-09-09 08:57:42 +00:00
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INIT_INI_ARRAY(&ah->iniModesAdditional,
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2024-09-09 08:52:07 +00:00
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ar9331_1p1_xtal_40M,
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ARRAY_SIZE(ar9331_1p1_xtal_40M), 2);
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} else if (AR_SREV_9330_12(ah)) {
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/* mac */
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
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ar9331_1p2_mac_core,
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ARRAY_SIZE(ar9331_1p2_mac_core), 2);
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
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ar9331_1p2_mac_postamble,
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ARRAY_SIZE(ar9331_1p2_mac_postamble), 5);
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/* bb */
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
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ar9331_1p2_baseband_core,
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ARRAY_SIZE(ar9331_1p2_baseband_core), 2);
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
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ar9331_1p2_baseband_postamble,
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ARRAY_SIZE(ar9331_1p2_baseband_postamble), 5);
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/* radio */
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
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ar9331_1p2_radio_core,
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ARRAY_SIZE(ar9331_1p2_radio_core), 2);
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], NULL, 0, 0);
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/* soc */
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
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ar9331_1p2_soc_preamble,
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ARRAY_SIZE(ar9331_1p2_soc_preamble), 2);
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
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ar9331_1p2_soc_postamble,
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ARRAY_SIZE(ar9331_1p2_soc_postamble), 2);
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/* rx/tx gain */
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INIT_INI_ARRAY(&ah->iniModesRxGain,
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ar9331_common_rx_gain_1p2,
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ARRAY_SIZE(ar9331_common_rx_gain_1p2), 2);
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9331_modes_lowest_ob_db_tx_gain_1p2,
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ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2),
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5);
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/* additional clock settings */
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if (ah->is_clk_25mhz)
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2024-09-09 08:57:42 +00:00
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INIT_INI_ARRAY(&ah->iniModesAdditional,
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2024-09-09 08:52:07 +00:00
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ar9331_1p2_xtal_25M,
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ARRAY_SIZE(ar9331_1p2_xtal_25M), 2);
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else
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2024-09-09 08:57:42 +00:00
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INIT_INI_ARRAY(&ah->iniModesAdditional,
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2024-09-09 08:52:07 +00:00
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ar9331_1p2_xtal_40M,
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ARRAY_SIZE(ar9331_1p2_xtal_40M), 2);
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} else if (AR_SREV_9340(ah)) {
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/* mac */
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
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ar9340_1p0_mac_core,
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ARRAY_SIZE(ar9340_1p0_mac_core), 2);
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
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ar9340_1p0_mac_postamble,
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ARRAY_SIZE(ar9340_1p0_mac_postamble), 5);
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/* bb */
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
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ar9340_1p0_baseband_core,
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ARRAY_SIZE(ar9340_1p0_baseband_core), 2);
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
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ar9340_1p0_baseband_postamble,
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ARRAY_SIZE(ar9340_1p0_baseband_postamble), 5);
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/* radio */
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
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ar9340_1p0_radio_core,
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ARRAY_SIZE(ar9340_1p0_radio_core), 2);
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
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ar9340_1p0_radio_postamble,
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ARRAY_SIZE(ar9340_1p0_radio_postamble), 5);
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/* soc */
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
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ar9340_1p0_soc_preamble,
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ARRAY_SIZE(ar9340_1p0_soc_preamble), 2);
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
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ar9340_1p0_soc_postamble,
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ARRAY_SIZE(ar9340_1p0_soc_postamble), 5);
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/* rx/tx gain */
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INIT_INI_ARRAY(&ah->iniModesRxGain,
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ar9340Common_wo_xlna_rx_gain_table_1p0,
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ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0),
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5);
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9340Modes_high_ob_db_tx_gain_table_1p0,
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ARRAY_SIZE(ar9340Modes_high_ob_db_tx_gain_table_1p0),
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5);
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2024-09-09 08:57:42 +00:00
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INIT_INI_ARRAY(&ah->iniModesAdditional,
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2024-09-09 08:52:07 +00:00
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ar9340Modes_fast_clock_1p0,
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ARRAY_SIZE(ar9340Modes_fast_clock_1p0),
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3);
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2024-09-09 08:57:42 +00:00
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INIT_INI_ARRAY(&ah->iniModesAdditional_40M,
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ar9340_1p0_radio_core_40M,
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ARRAY_SIZE(ar9340_1p0_radio_core_40M),
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2);
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2024-09-09 08:52:07 +00:00
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} else if (AR_SREV_9485_11(ah)) {
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/* mac */
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
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ar9485_1_1_mac_core,
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ARRAY_SIZE(ar9485_1_1_mac_core), 2);
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
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ar9485_1_1_mac_postamble,
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ARRAY_SIZE(ar9485_1_1_mac_postamble), 5);
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/* bb */
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1,
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ARRAY_SIZE(ar9485_1_1), 2);
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
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ar9485_1_1_baseband_core,
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ARRAY_SIZE(ar9485_1_1_baseband_core), 2);
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
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ar9485_1_1_baseband_postamble,
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ARRAY_SIZE(ar9485_1_1_baseband_postamble), 5);
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/* radio */
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
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ar9485_1_1_radio_core,
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ARRAY_SIZE(ar9485_1_1_radio_core), 2);
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
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ar9485_1_1_radio_postamble,
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ARRAY_SIZE(ar9485_1_1_radio_postamble), 2);
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/* soc */
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
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ar9485_1_1_soc_preamble,
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ARRAY_SIZE(ar9485_1_1_soc_preamble), 2);
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], NULL, 0, 0);
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/* rx/tx gain */
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INIT_INI_ARRAY(&ah->iniModesRxGain,
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ar9485Common_wo_xlna_rx_gain_1_1,
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ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1), 2);
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9485_modes_lowest_ob_db_tx_gain_1_1,
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ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
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5);
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/* Load PCIE SERDES settings from INI */
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/* Awake Setting */
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INIT_INI_ARRAY(&ah->iniPcieSerdes,
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ar9485_1_1_pcie_phy_clkreq_disable_L1,
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ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
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2);
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/* Sleep Setting */
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INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
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ar9485_1_1_pcie_phy_clkreq_disable_L1,
|
|
|
|
|
ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
|
|
|
|
|
2);
|
2024-09-09 08:57:42 +00:00
|
|
|
} else if (AR_SREV_9462_10(ah)) {
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_1p0_mac_core,
|
|
|
|
|
ARRAY_SIZE(ar9462_1p0_mac_core), 2);
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
|
|
|
|
|
ar9462_1p0_mac_postamble,
|
|
|
|
|
ARRAY_SIZE(ar9462_1p0_mac_postamble),
|
|
|
|
|
5);
|
|
|
|
|
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
|
|
|
|
|
ar9462_1p0_baseband_core,
|
|
|
|
|
ARRAY_SIZE(ar9462_1p0_baseband_core),
|
|
|
|
|
2);
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
|
|
|
|
|
ar9462_1p0_baseband_postamble,
|
|
|
|
|
ARRAY_SIZE(ar9462_1p0_baseband_postamble), 5);
|
|
|
|
|
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
|
|
|
|
|
ar9462_1p0_radio_core,
|
|
|
|
|
ARRAY_SIZE(ar9462_1p0_radio_core), 2);
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
|
|
|
|
|
ar9462_1p0_radio_postamble,
|
|
|
|
|
ARRAY_SIZE(ar9462_1p0_radio_postamble), 5);
|
|
|
|
|
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
|
|
|
|
|
ar9462_1p0_soc_preamble,
|
|
|
|
|
ARRAY_SIZE(ar9462_1p0_soc_preamble), 2);
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
|
|
|
|
|
ar9462_1p0_soc_postamble,
|
|
|
|
|
ARRAY_SIZE(ar9462_1p0_soc_postamble), 5);
|
|
|
|
|
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
|
|
|
ar9462_common_rx_gain_table_1p0,
|
|
|
|
|
ARRAY_SIZE(ar9462_common_rx_gain_table_1p0), 2);
|
|
|
|
|
|
|
|
|
|
/* Awake -> Sleep Setting */
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniPcieSerdes,
|
|
|
|
|
ar9462_pcie_phy_clkreq_disable_L1_1p0,
|
|
|
|
|
ARRAY_SIZE(ar9462_pcie_phy_clkreq_disable_L1_1p0),
|
|
|
|
|
2);
|
|
|
|
|
|
|
|
|
|
/* Sleep -> Awake Setting */
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
|
|
|
|
|
ar9462_pcie_phy_clkreq_disable_L1_1p0,
|
|
|
|
|
ARRAY_SIZE(ar9462_pcie_phy_clkreq_disable_L1_1p0),
|
|
|
|
|
2);
|
|
|
|
|
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesAdditional,
|
|
|
|
|
ar9462_modes_fast_clock_1p0,
|
|
|
|
|
ARRAY_SIZE(ar9462_modes_fast_clock_1p0), 3);
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
|
|
|
|
|
AR9462_BB_CTX_COEFJ(1p0),
|
|
|
|
|
ARRAY_SIZE(AR9462_BB_CTX_COEFJ(1p0)), 2);
|
|
|
|
|
|
2024-09-09 08:52:07 +00:00
|
|
|
} else if (AR_SREV_9462_20(ah)) {
|
|
|
|
|
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core,
|
|
|
|
|
ARRAY_SIZE(ar9462_2p0_mac_core), 2);
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
|
|
|
|
|
ar9462_2p0_mac_postamble,
|
|
|
|
|
ARRAY_SIZE(ar9462_2p0_mac_postamble), 5);
|
|
|
|
|
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
|
|
|
|
|
ar9462_2p0_baseband_core,
|
|
|
|
|
ARRAY_SIZE(ar9462_2p0_baseband_core), 2);
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
|
|
|
|
|
ar9462_2p0_baseband_postamble,
|
|
|
|
|
ARRAY_SIZE(ar9462_2p0_baseband_postamble), 5);
|
|
|
|
|
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
|
|
|
|
|
ar9462_2p0_radio_core,
|
|
|
|
|
ARRAY_SIZE(ar9462_2p0_radio_core), 2);
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
|
|
|
|
|
ar9462_2p0_radio_postamble,
|
|
|
|
|
ARRAY_SIZE(ar9462_2p0_radio_postamble), 5);
|
|
|
|
|
INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant,
|
|
|
|
|
ar9462_2p0_radio_postamble_sys2ant,
|
|
|
|
|
ARRAY_SIZE(ar9462_2p0_radio_postamble_sys2ant),
|
|
|
|
|
5);
|
|
|
|
|
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
|
|
|
|
|
ar9462_2p0_soc_preamble,
|
|
|
|
|
ARRAY_SIZE(ar9462_2p0_soc_preamble), 2);
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
|
|
|
|
|
ar9462_2p0_soc_postamble,
|
|
|
|
|
ARRAY_SIZE(ar9462_2p0_soc_postamble), 5);
|
|
|
|
|
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
|
|
|
ar9462_common_rx_gain_table_2p0,
|
|
|
|
|
ARRAY_SIZE(ar9462_common_rx_gain_table_2p0), 2);
|
|
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
INIT_INI_ARRAY(&ah->ini_BTCOEX_MAX_TXPWR,
|
|
|
|
|
ar9462_2p0_BTCOEX_MAX_TXPWR_table,
|
|
|
|
|
ARRAY_SIZE(ar9462_2p0_BTCOEX_MAX_TXPWR_table),
|
|
|
|
|
2);
|
|
|
|
|
|
2024-09-09 08:52:07 +00:00
|
|
|
/* Awake -> Sleep Setting */
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniPcieSerdes,
|
|
|
|
|
PCIE_PLL_ON_CREQ_DIS_L1_2P0,
|
|
|
|
|
ARRAY_SIZE(PCIE_PLL_ON_CREQ_DIS_L1_2P0),
|
|
|
|
|
2);
|
|
|
|
|
/* Sleep -> Awake Setting */
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
|
|
|
|
|
PCIE_PLL_ON_CREQ_DIS_L1_2P0,
|
|
|
|
|
ARRAY_SIZE(PCIE_PLL_ON_CREQ_DIS_L1_2P0),
|
|
|
|
|
2);
|
|
|
|
|
|
|
|
|
|
/* Fast clock modal settings */
|
2024-09-09 08:57:42 +00:00
|
|
|
INIT_INI_ARRAY(&ah->iniModesAdditional,
|
2024-09-09 08:52:07 +00:00
|
|
|
ar9462_modes_fast_clock_2p0,
|
|
|
|
|
ARRAY_SIZE(ar9462_modes_fast_clock_2p0), 3);
|
|
|
|
|
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
|
|
|
|
|
AR9462_BB_CTX_COEFJ(2p0),
|
|
|
|
|
ARRAY_SIZE(AR9462_BB_CTX_COEFJ(2p0)), 2);
|
|
|
|
|
|
|
|
|
|
INIT_INI_ARRAY(&ah->ini_japan2484, AR9462_BBC_TXIFR_COEFFJ,
|
|
|
|
|
ARRAY_SIZE(AR9462_BBC_TXIFR_COEFFJ), 2);
|
|
|
|
|
|
|
|
|
|
} else if (AR_SREV_9580(ah)) {
|
|
|
|
|
/* mac */
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
|
|
|
|
|
ar9580_1p0_mac_core,
|
|
|
|
|
ARRAY_SIZE(ar9580_1p0_mac_core), 2);
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
|
|
|
|
|
ar9580_1p0_mac_postamble,
|
|
|
|
|
ARRAY_SIZE(ar9580_1p0_mac_postamble), 5);
|
|
|
|
|
|
|
|
|
|
/* bb */
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
|
|
|
|
|
ar9580_1p0_baseband_core,
|
|
|
|
|
ARRAY_SIZE(ar9580_1p0_baseband_core), 2);
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
|
|
|
|
|
ar9580_1p0_baseband_postamble,
|
|
|
|
|
ARRAY_SIZE(ar9580_1p0_baseband_postamble), 5);
|
|
|
|
|
|
|
|
|
|
/* radio */
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
|
|
|
|
|
ar9580_1p0_radio_core,
|
|
|
|
|
ARRAY_SIZE(ar9580_1p0_radio_core), 2);
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
|
|
|
|
|
ar9580_1p0_radio_postamble,
|
|
|
|
|
ARRAY_SIZE(ar9580_1p0_radio_postamble), 5);
|
|
|
|
|
|
|
|
|
|
/* soc */
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
|
|
|
|
|
ar9580_1p0_soc_preamble,
|
|
|
|
|
ARRAY_SIZE(ar9580_1p0_soc_preamble), 2);
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
|
|
|
|
|
ar9580_1p0_soc_postamble,
|
|
|
|
|
ARRAY_SIZE(ar9580_1p0_soc_postamble), 5);
|
|
|
|
|
|
|
|
|
|
/* rx/tx gain */
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
|
|
|
ar9580_1p0_rx_gain_table,
|
|
|
|
|
ARRAY_SIZE(ar9580_1p0_rx_gain_table), 2);
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
|
|
ar9580_1p0_low_ob_db_tx_gain_table,
|
|
|
|
|
ARRAY_SIZE(ar9580_1p0_low_ob_db_tx_gain_table),
|
|
|
|
|
5);
|
|
|
|
|
|
2024-09-09 08:57:42 +00:00
|
|
|
INIT_INI_ARRAY(&ah->iniModesAdditional,
|
2024-09-09 08:52:07 +00:00
|
|
|
ar9580_1p0_modes_fast_clock,
|
|
|
|
|
ARRAY_SIZE(ar9580_1p0_modes_fast_clock),
|
|
|
|
|
3);
|
|
|
|
|
} else {
|
|
|
|
|
/* mac */
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
|
|
|
|
|
ar9300_2p2_mac_core,
|
|
|
|
|
ARRAY_SIZE(ar9300_2p2_mac_core), 2);
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
|
|
|
|
|
ar9300_2p2_mac_postamble,
|
|
|
|
|
ARRAY_SIZE(ar9300_2p2_mac_postamble), 5);
|
|
|
|
|
|
|
|
|
|
/* bb */
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
|
|
|
|
|
ar9300_2p2_baseband_core,
|
|
|
|
|
ARRAY_SIZE(ar9300_2p2_baseband_core), 2);
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
|
|
|
|
|
ar9300_2p2_baseband_postamble,
|
|
|
|
|
ARRAY_SIZE(ar9300_2p2_baseband_postamble), 5);
|
|
|
|
|
|
|
|
|
|
/* radio */
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
|
|
|
|
|
ar9300_2p2_radio_core,
|
|
|
|
|
ARRAY_SIZE(ar9300_2p2_radio_core), 2);
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
|
|
|
|
|
ar9300_2p2_radio_postamble,
|
|
|
|
|
ARRAY_SIZE(ar9300_2p2_radio_postamble), 5);
|
|
|
|
|
|
|
|
|
|
/* soc */
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
|
|
|
|
|
ar9300_2p2_soc_preamble,
|
|
|
|
|
ARRAY_SIZE(ar9300_2p2_soc_preamble), 2);
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
|
|
|
|
|
ar9300_2p2_soc_postamble,
|
|
|
|
|
ARRAY_SIZE(ar9300_2p2_soc_postamble), 5);
|
|
|
|
|
|
|
|
|
|
/* rx/tx gain */
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
|
|
|
ar9300Common_rx_gain_table_2p2,
|
|
|
|
|
ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), 2);
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
|
|
ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
|
|
|
|
|
ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
|
|
|
|
|
5);
|
|
|
|
|
|
|
|
|
|
/* Load PCIE SERDES settings from INI */
|
|
|
|
|
|
|
|
|
|
/* Awake Setting */
|
|
|
|
|
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniPcieSerdes,
|
|
|
|
|
ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
|
|
|
|
|
ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
|
|
|
|
|
2);
|
|
|
|
|
|
|
|
|
|
/* Sleep Setting */
|
|
|
|
|
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
|
|
|
|
|
ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
|
|
|
|
|
ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
|
|
|
|
|
2);
|
|
|
|
|
|
|
|
|
|
/* Fast clock modal settings */
|
2024-09-09 08:57:42 +00:00
|
|
|
INIT_INI_ARRAY(&ah->iniModesAdditional,
|
2024-09-09 08:52:07 +00:00
|
|
|
ar9300Modes_fast_clock_2p2,
|
|
|
|
|
ARRAY_SIZE(ar9300Modes_fast_clock_2p2),
|
|
|
|
|
3);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void ar9003_tx_gain_table_mode0(struct ath_hw *ah)
|
|
|
|
|
{
|
|
|
|
|
if (AR_SREV_9330_12(ah))
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
|
|
ar9331_modes_lowest_ob_db_tx_gain_1p2,
|
|
|
|
|
ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2),
|
|
|
|
|
5);
|
|
|
|
|
else if (AR_SREV_9330_11(ah))
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
|
|
ar9331_modes_lowest_ob_db_tx_gain_1p1,
|
|
|
|
|
ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1),
|
|
|
|
|
5);
|
|
|
|
|
else if (AR_SREV_9340(ah))
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
|
|
ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
|
|
|
|
|
ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
|
|
|
|
|
5);
|
|
|
|
|
else if (AR_SREV_9485_11(ah))
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
|
|
ar9485_modes_lowest_ob_db_tx_gain_1_1,
|
|
|
|
|
ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
|
|
|
|
|
5);
|
|
|
|
|
else if (AR_SREV_9580(ah))
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
|
|
ar9580_1p0_lowest_ob_db_tx_gain_table,
|
|
|
|
|
ARRAY_SIZE(ar9580_1p0_lowest_ob_db_tx_gain_table),
|
|
|
|
|
5);
|
2024-09-09 08:57:42 +00:00
|
|
|
else if (AR_SREV_9462_10(ah))
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
|
|
ar9462_modes_low_ob_db_tx_gain_table_1p0,
|
|
|
|
|
ARRAY_SIZE(ar9462_modes_low_ob_db_tx_gain_table_1p0),
|
|
|
|
|
5);
|
2024-09-09 08:52:07 +00:00
|
|
|
else if (AR_SREV_9462_20(ah))
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
|
|
ar9462_modes_low_ob_db_tx_gain_table_2p0,
|
|
|
|
|
ARRAY_SIZE(ar9462_modes_low_ob_db_tx_gain_table_2p0),
|
|
|
|
|
5);
|
|
|
|
|
else
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
|
|
ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
|
|
|
|
|
ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
|
|
|
|
|
5);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void ar9003_tx_gain_table_mode1(struct ath_hw *ah)
|
|
|
|
|
{
|
|
|
|
|
if (AR_SREV_9330_12(ah))
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
|
|
ar9331_modes_high_ob_db_tx_gain_1p2,
|
|
|
|
|
ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p2),
|
|
|
|
|
5);
|
|
|
|
|
else if (AR_SREV_9330_11(ah))
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
|
|
ar9331_modes_high_ob_db_tx_gain_1p1,
|
|
|
|
|
ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p1),
|
|
|
|
|
5);
|
|
|
|
|
else if (AR_SREV_9340(ah))
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
|
|
ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
|
|
|
|
|
ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
|
|
|
|
|
5);
|
|
|
|
|
else if (AR_SREV_9485_11(ah))
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
|
|
ar9485Modes_high_ob_db_tx_gain_1_1,
|
|
|
|
|
ARRAY_SIZE(ar9485Modes_high_ob_db_tx_gain_1_1),
|
|
|
|
|
5);
|
|
|
|
|
else if (AR_SREV_9580(ah))
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
|
|
ar9580_1p0_high_ob_db_tx_gain_table,
|
|
|
|
|
ARRAY_SIZE(ar9580_1p0_high_ob_db_tx_gain_table),
|
|
|
|
|
5);
|
2024-09-09 08:57:42 +00:00
|
|
|
else if (AR_SREV_9462_10(ah))
|
2024-09-09 08:52:07 +00:00
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
2024-09-09 08:57:42 +00:00
|
|
|
ar9462_modes_high_ob_db_tx_gain_table_1p0,
|
|
|
|
|
ARRAY_SIZE(ar9462_modes_high_ob_db_tx_gain_table_1p0),
|
|
|
|
|
5);
|
2024-09-09 08:52:07 +00:00
|
|
|
else if (AR_SREV_9462_20(ah))
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
|
|
ar9462_modes_high_ob_db_tx_gain_table_2p0,
|
|
|
|
|
ARRAY_SIZE(ar9462_modes_high_ob_db_tx_gain_table_2p0),
|
|
|
|
|
5);
|
|
|
|
|
else
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
|
|
ar9300Modes_high_ob_db_tx_gain_table_2p2,
|
|
|
|
|
ARRAY_SIZE(ar9300Modes_high_ob_db_tx_gain_table_2p2),
|
|
|
|
|
5);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void ar9003_tx_gain_table_mode2(struct ath_hw *ah)
|
|
|
|
|
{
|
|
|
|
|
if (AR_SREV_9330_12(ah))
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
|
|
ar9331_modes_low_ob_db_tx_gain_1p2,
|
|
|
|
|
ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p2),
|
|
|
|
|
5);
|
|
|
|
|
else if (AR_SREV_9330_11(ah))
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
|
|
ar9331_modes_low_ob_db_tx_gain_1p1,
|
|
|
|
|
ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p1),
|
|
|
|
|
5);
|
|
|
|
|
else if (AR_SREV_9340(ah))
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
|
|
ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
|
|
|
|
|
ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
|
|
|
|
|
5);
|
|
|
|
|
else if (AR_SREV_9485_11(ah))
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
|
|
ar9485Modes_low_ob_db_tx_gain_1_1,
|
|
|
|
|
ARRAY_SIZE(ar9485Modes_low_ob_db_tx_gain_1_1),
|
|
|
|
|
5);
|
|
|
|
|
else if (AR_SREV_9580(ah))
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
|
|
ar9580_1p0_low_ob_db_tx_gain_table,
|
|
|
|
|
ARRAY_SIZE(ar9580_1p0_low_ob_db_tx_gain_table),
|
|
|
|
|
5);
|
|
|
|
|
else
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
|
|
ar9300Modes_low_ob_db_tx_gain_table_2p2,
|
|
|
|
|
ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p2),
|
|
|
|
|
5);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void ar9003_tx_gain_table_mode3(struct ath_hw *ah)
|
|
|
|
|
{
|
|
|
|
|
if (AR_SREV_9330_12(ah))
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
|
|
ar9331_modes_high_power_tx_gain_1p2,
|
|
|
|
|
ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p2),
|
|
|
|
|
5);
|
|
|
|
|
else if (AR_SREV_9330_11(ah))
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
|
|
ar9331_modes_high_power_tx_gain_1p1,
|
|
|
|
|
ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p1),
|
|
|
|
|
5);
|
|
|
|
|
else if (AR_SREV_9340(ah))
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
|
|
ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
|
|
|
|
|
ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
|
|
|
|
|
5);
|
|
|
|
|
else if (AR_SREV_9485_11(ah))
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
|
|
ar9485Modes_high_power_tx_gain_1_1,
|
|
|
|
|
ARRAY_SIZE(ar9485Modes_high_power_tx_gain_1_1),
|
|
|
|
|
5);
|
|
|
|
|
else if (AR_SREV_9580(ah))
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
|
|
ar9580_1p0_high_power_tx_gain_table,
|
|
|
|
|
ARRAY_SIZE(ar9580_1p0_high_power_tx_gain_table),
|
|
|
|
|
5);
|
|
|
|
|
else
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesTxGain,
|
|
|
|
|
ar9300Modes_high_power_tx_gain_table_2p2,
|
|
|
|
|
ARRAY_SIZE(ar9300Modes_high_power_tx_gain_table_2p2),
|
|
|
|
|
5);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
|
|
|
|
|
{
|
|
|
|
|
switch (ar9003_hw_get_tx_gain_idx(ah)) {
|
|
|
|
|
case 0:
|
|
|
|
|
default:
|
|
|
|
|
ar9003_tx_gain_table_mode0(ah);
|
|
|
|
|
break;
|
|
|
|
|
case 1:
|
|
|
|
|
ar9003_tx_gain_table_mode1(ah);
|
|
|
|
|
break;
|
|
|
|
|
case 2:
|
|
|
|
|
ar9003_tx_gain_table_mode2(ah);
|
|
|
|
|
break;
|
|
|
|
|
case 3:
|
|
|
|
|
ar9003_tx_gain_table_mode3(ah);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void ar9003_rx_gain_table_mode0(struct ath_hw *ah)
|
|
|
|
|
{
|
|
|
|
|
if (AR_SREV_9330_12(ah))
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
|
|
|
ar9331_common_rx_gain_1p2,
|
|
|
|
|
ARRAY_SIZE(ar9331_common_rx_gain_1p2),
|
|
|
|
|
2);
|
|
|
|
|
else if (AR_SREV_9330_11(ah))
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
|
|
|
ar9331_common_rx_gain_1p1,
|
|
|
|
|
ARRAY_SIZE(ar9331_common_rx_gain_1p1),
|
|
|
|
|
2);
|
|
|
|
|
else if (AR_SREV_9340(ah))
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
|
|
|
ar9340Common_rx_gain_table_1p0,
|
|
|
|
|
ARRAY_SIZE(ar9340Common_rx_gain_table_1p0),
|
|
|
|
|
2);
|
|
|
|
|
else if (AR_SREV_9485_11(ah))
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
|
|
|
ar9485Common_wo_xlna_rx_gain_1_1,
|
|
|
|
|
ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
|
|
|
|
|
2);
|
2024-09-09 08:57:42 +00:00
|
|
|
else if (AR_SREV_9580(ah))
|
2024-09-09 08:52:07 +00:00
|
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
|
|
|
ar9580_1p0_rx_gain_table,
|
|
|
|
|
ARRAY_SIZE(ar9580_1p0_rx_gain_table),
|
|
|
|
|
2);
|
2024-09-09 08:57:42 +00:00
|
|
|
else if (AR_SREV_9462_10(ah))
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
|
|
|
ar9462_common_rx_gain_table_1p0,
|
|
|
|
|
ARRAY_SIZE(ar9462_common_rx_gain_table_1p0),
|
|
|
|
|
2);
|
2024-09-09 08:52:07 +00:00
|
|
|
else if (AR_SREV_9462_20(ah))
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
|
|
|
ar9462_common_rx_gain_table_2p0,
|
|
|
|
|
ARRAY_SIZE(ar9462_common_rx_gain_table_2p0),
|
|
|
|
|
2);
|
|
|
|
|
else
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
|
|
|
ar9300Common_rx_gain_table_2p2,
|
|
|
|
|
ARRAY_SIZE(ar9300Common_rx_gain_table_2p2),
|
|
|
|
|
2);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void ar9003_rx_gain_table_mode1(struct ath_hw *ah)
|
|
|
|
|
{
|
|
|
|
|
if (AR_SREV_9330_12(ah))
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
|
|
|
ar9331_common_wo_xlna_rx_gain_1p2,
|
|
|
|
|
ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p2),
|
|
|
|
|
2);
|
|
|
|
|
else if (AR_SREV_9330_11(ah))
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
|
|
|
ar9331_common_wo_xlna_rx_gain_1p1,
|
|
|
|
|
ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p1),
|
|
|
|
|
2);
|
|
|
|
|
else if (AR_SREV_9340(ah))
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
|
|
|
ar9340Common_wo_xlna_rx_gain_table_1p0,
|
|
|
|
|
ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0),
|
|
|
|
|
2);
|
|
|
|
|
else if (AR_SREV_9485_11(ah))
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
|
|
|
ar9485Common_wo_xlna_rx_gain_1_1,
|
|
|
|
|
ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
|
|
|
|
|
2);
|
2024-09-09 08:57:42 +00:00
|
|
|
else if (AR_SREV_9462_10(ah))
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
|
|
|
ar9462_common_wo_xlna_rx_gain_table_1p0,
|
|
|
|
|
ARRAY_SIZE(ar9462_common_wo_xlna_rx_gain_table_1p0),
|
|
|
|
|
2);
|
2024-09-09 08:52:07 +00:00
|
|
|
else if (AR_SREV_9462_20(ah))
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
|
|
|
ar9462_common_wo_xlna_rx_gain_table_2p0,
|
|
|
|
|
ARRAY_SIZE(ar9462_common_wo_xlna_rx_gain_table_2p0),
|
|
|
|
|
2);
|
2024-09-09 08:57:42 +00:00
|
|
|
else if (AR_SREV_9580(ah))
|
2024-09-09 08:52:07 +00:00
|
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
|
|
|
ar9580_1p0_wo_xlna_rx_gain_table,
|
|
|
|
|
ARRAY_SIZE(ar9580_1p0_wo_xlna_rx_gain_table),
|
|
|
|
|
2);
|
|
|
|
|
else
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
|
|
|
ar9300Common_wo_xlna_rx_gain_table_2p2,
|
|
|
|
|
ARRAY_SIZE(ar9300Common_wo_xlna_rx_gain_table_2p2),
|
|
|
|
|
2);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void ar9003_rx_gain_table_mode2(struct ath_hw *ah)
|
|
|
|
|
{
|
2024-09-09 08:57:42 +00:00
|
|
|
if (AR_SREV_9462_10(ah))
|
|
|
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
|
|
|
|
ar9462_common_mixed_rx_gain_table_1p0,
|
|
|
|
|
ARRAY_SIZE(ar9462_common_mixed_rx_gain_table_1p0), 2);
|
|
|
|
|
else if (AR_SREV_9462_20(ah))
|
2024-09-09 08:52:07 +00:00
|
|
|
INIT_INI_ARRAY(&ah->iniModesRxGain,
|
2024-09-09 08:57:42 +00:00
|
|
|
ar9462_common_mixed_rx_gain_table_2p0,
|
|
|
|
|
ARRAY_SIZE(ar9462_common_mixed_rx_gain_table_2p0), 2);
|
2024-09-09 08:52:07 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
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{
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switch (ar9003_hw_get_rx_gain_idx(ah)) {
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case 0:
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default:
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ar9003_rx_gain_table_mode0(ah);
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break;
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case 1:
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ar9003_rx_gain_table_mode1(ah);
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break;
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case 2:
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ar9003_rx_gain_table_mode2(ah);
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break;
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}
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}
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/* set gain table pointers according to values read from the eeprom */
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static void ar9003_hw_init_mode_gain_regs(struct ath_hw *ah)
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{
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ar9003_tx_gain_table_apply(ah);
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ar9003_rx_gain_table_apply(ah);
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}
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/*
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* Helper for ASPM support.
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*
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* Disable PLL when in L0s as well as receiver clock when in L1.
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* This power saving option must be enabled through the SerDes.
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*
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* Programming the SerDes must go through the same 288 bit serial shift
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* register as the other analog registers. Hence the 9 writes.
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*/
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static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
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bool power_off)
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{
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/* Nothing to do on restore for 11N */
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if (!power_off /* !restore */) {
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/* set bit 19 to allow forcing of pcie core into L1 state */
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REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
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/* Several PCIe massages to ensure proper behaviour */
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if (ah->config.pcie_waen)
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REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
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else
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REG_WRITE(ah, AR_WA, ah->WARegVal);
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}
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/*
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* Configire PCIE after Ini init. SERDES values now come from ini file
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* This enables PCIe low power mode.
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*/
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if (ah->config.pcieSerDesWrite) {
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unsigned int i;
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struct ar5416IniArray *array;
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array = power_off ? &ah->iniPcieSerdes :
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&ah->iniPcieSerdesLowPower;
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for (i = 0; i < array->ia_rows; i++) {
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REG_WRITE(ah,
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INI_RA(array, i, 0),
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INI_RA(array, i, 1));
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}
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}
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}
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/* Sets up the AR9003 hardware familiy callbacks */
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void ar9003_hw_attach_ops(struct ath_hw *ah)
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{
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struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
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struct ath_hw_ops *ops = ath9k_hw_ops(ah);
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priv_ops->init_mode_regs = ar9003_hw_init_mode_regs;
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priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs;
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ops->config_pci_powersave = ar9003_hw_configpcipowersave;
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ar9003_hw_attach_phy_ops(ah);
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ar9003_hw_attach_calib_ops(ah);
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ar9003_hw_attach_mac_ops(ah);
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}
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